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3 дня назад

IC Design Engineer (SerDes)

141 300 - 226 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR

IC Design Engineer (SerDes): Designing and optimizing digital portions of high-performance SerDes IP for next-generation communication systems with an accent on architecture understanding, design, simulation, and optimization of digital components. Focus on analyzing and resolving Lint and Clock/Reset Domain crossing issues, ensuring robust signal and power integrity, and supporting silicon bring-up and debug efforts.

Location: Onsite in San Jose, CA or Irvine, CA, USA.

Salary: $141,300–$226,000 annually.

Company

hirify.global is a global technology leader designing, developing, and supplying semiconductor and infrastructure software solutions.

What you will do

  • Understand the architecture of SerDes transmitters, receivers, equalizers, and clock recovery circuits.
  • Design, simulate, and optimize SerDes-related digital components considering data rate, jitter, and power.
  • Analyze and resolve Lint and Clock/Reset Domain crossing issues.
  • Collaborate with engineering teams for robust signal and power integrity.
  • Integrate SerDes IP into larger systems with cross-functional teams.
  • Prepare and maintain comprehensive design documentation.
  • Support silicon bring-up and debug efforts.

Requirements

  • BS degree +12 years of relevant industry experience (advanced degree preferred).
  • Proven experience in SerDes design with a focus on high-speed communication interfaces.
  • Strong Logic Design and RTL coding (Verilog HDL) skills.
  • Familiarity with analog and mixed-signal circuit design principles.
  • Understanding of process technologies impact on SerDes design.
  • Familiarity with system-level considerations in high-speed communication interfaces.
  • Knowledge of low power design and validation techniques, including UPF.
  • Familiarity with design constraint generation, logic synthesis, timing closure analysis, and Clock/Reset domain crossing checks.

Culture & Benefits

  • Competitive and comprehensive benefits package including Medical, Dental, Vision plans, and 401(K) with company matching.
  • Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
  • Company paid holidays, paid sick leave, and vacation time.
  • Opportunity to work with remote and cross-functional teams.
  • Self-motivated and independent work environment.

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