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3 дня назад

Senior Staff Engineer, Analog Layout

118 190 - 177 100$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Senior Staff Engineer, Analog Layout: Designing and optimizing analog mixed-signal layouts for high-speed connectivity and data transport products with an accent on deep sub-micron CMOS technologies and verification processes. Focus on floor planning, custom layout, and ensuring compliance with design rules like DRC, LVS, and ESD.

Location: Santa Clara, CA

Salary: $118,190 - $177,100 per annum

Company

hirify.global provides semiconductor solutions that are essential building blocks for the data infrastructure connecting our world, enabling new possibilities across enterprise, cloud, AI, automotive, and carrier architectures.

What you will do

  • Design and optimize analog mixed-signal layouts (ADCs, PLLs, LDOs, I/Os, ESD) in deep sub-micron CMOS using Cadence or Synopsys tools.
  • Collaborate closely with circuit designers and other teams to meet project specifications and timelines.
  • Perform floor planning, custom layout, and verify compliance with design rules including DRC, LVS, ANT, LUP, ESD, and PERC.
  • Maintain detailed documentation of layout methodologies, design decisions, and verification results.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 3-5+ years of relevant professional experience.
  • Experience in analog/mixed-signal layout design for deep sub-micron CMOS circuits.
  • Proficiency in block-level floor planning and capable of driving the project through tape-out.
  • Experience with CAD tools such as Cadence "Virtuoso," Mentor Graphics "Calibre," or Synopsys "Custom Compiler."
  • Strong proficiency in interpreting DRC, ERC, LVS, LUP, and PERC reports.
  • Applicants must be eligible to access export-controlled information as defined under applicable U.S. export control laws and regulations.

Nice to have

  • Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 2-3+ years of experience.
  • Familiarity with advanced process technologies and FinFET.
  • Proficiency in chip-level floor planning.

Culture & Benefits

  • Total compensation package with a base, bonus, and equity.
  • Health and financial wellbeing benefits including flexible time off, 401k, year-end shutdown, floating holidays, and paid time off to volunteer.
  • Commitment to fair and authentic hiring practices, strictly prohibiting the use of AI tools during interviews.

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