Rf/Analog Asic Layout Engineer

TL;DR

Rf/Analog Asic Layout Engineer: Physical design and layout of RF/Analog SiGe BiCMOS circuit modules with an accent on Cadence Virtuoso XL and full verification flow. Focus on floor-planning, scripting, and tape out procedures in close collaboration with design and system teams.

Company

hirify.global is a global technology company with approximately 15,000 employees, specializing in Test & Measurement, Technology Systems, and Networks & Cybersecurity, pushing technological boundaries for 90 years.

What you will do

• Physically design RF/Analog SiGe BiCMOS circuit modules using Cadence Virtuoso XL.
• Perform block level layout and full verification flow (DRC, LVS) with Cadence Assura/PVS tools.
• Collaborate on floor-planning with RF IC design and RF system teams.
• Develop scripts for tasks using Skill and Python.
• Manage tape out procedures.

Requirements

• Bachelor's or Master's degree in Electrical Engineering or related field.
• Several years of custom RF/analog layout experience with SiGe BiCMOS processes.
• In-depth knowledge of layout techniques for device matching, parasitic reduction, RF shielding, and high frequency routing.
• Deep understanding of design flow from schematic to GDSII including verification and process design kits.
• Good communication skills in English and German.