aistartupsimulationsystemveriloguvmformal verificationsilicon validationassertion based verificationcoverage closure
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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$240к/год
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Зона ответственности четко охватывает планирование и реализацию верификации, закрытие покрытия и подготовку кремния к sign-off, а работа связана с AI-ускорителями.
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Hirify AI/Оригинал
TL;DR
Design Verification Engineer (AI Accelerator Silicon): Building rigorous verification environments, tests, models, and assertions for AI accelerator silicon spanning compute, memory management, and high-speed connectivity with an accent on SystemVerilog, UVM, simulation, formal verification, and coverage closure. Focus on diagnosing cross-boundary failures, developing portable pre-silicon and post-silicon tests, and establishing technical evidence for sign-off decisions.
Location: Mountain View or remote in the United States
Salary: $240,000 per year
Company
hirify.global is partnering with an AI compute startup building a full-stack platform for large-scale AI workloads.
What you will do
Translate architectural and design specifications into verification plans, testbenches, tests, models, and reusable infrastructure.
Develop SystemVerilog and UVM environments, assertion-based checks, and portable tests or drivers.
Use simulation and formal verification to investigate functional behavior, corner cases, and failures across testbench, model, and RTL boundaries.
Drive structural and functional coverage closure, identify missing scenarios, diagnose failures, and prioritize further verification work.
Contribute to sign-off decisions and verification reviews by reporting coverage gaps, remaining risks, and milestone readiness.
Collaborate with architecture, RTL, and validation engineers across the silicon lifecycle.
Requirements
Personal ownership of verification implementation and delivery for complex silicon blocks, subsystems, or SoCs.
Production experience with SystemVerilog, UVM, and assertion-based verification, with comfort using formal and simulation methods.
Strong debugging skills and the ability to connect failures to microarchitectural behavior.
Experience closing coverage and explaining the technical evidence behind verification milestones.
Understanding of compute, memory-management, or connectivity microarchitecture and its impact on verification choices.
Programming or modeling skills supporting test development, reference behavior, automation, and failure analysis.
Ability to justify coverage and closure decisions using technical evidence, including exercised behavior and remaining risks.
Nice to have
Experience verifying CPUs, GPUs, accelerators, memory controllers, or complex connectivity with comparable ownership of implementation and closure.
Emulation, prototyping, silicon validation, or bring-up experience connecting pre-silicon tests to hardware behavior.
Experience creating portable tests, drivers, or reusable infrastructure across blocks and development stages.
Culture & Benefits
Remote work is available for the role, with Mountain View listed as an alternative location.
Engineers at multiple career levels are considered; scope and complexity of owned work matter more than fixed tenure.
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