pythonunixsystemveriloguvmedafunctional coverageconstrained random verificationsystemverilog assertionssoc design verification
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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$106к-184к/год
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Чётко очерченная роль Staff-инженера в крупной полупроводниковой компании предполагает самостоятельную ответственность и техническое лидерство, а требования и задачи описаны конкретно.
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Чёткая зона ответственности
Крупный игрок отрасли
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Hirify AI/Оригинал
TL;DR
SoC Design Verification Engineer (SystemVerilog/UVM): Verifying custom System-on-Chip designs through reusable testbenches, assertions, checkers, scoreboards, and coverage models with an accent on complex verification planning, stimulus development, and signoff closure. Focus on analyzing logs and waveforms, resolving novel design failures, improving verification automation, and guiding other engineers.
Location: Richardson, United States of America
Expected salary: $106,000.00–$184,000.00 per year
Company
hirify.global is a full-service semiconductor foundry providing design, development, and fabrication services with a global manufacturing footprint.
What you will do
Review SoC architecture and design specifications to derive verification requirements, risks, and test scenarios.
Develop and own verification plans for complex blocks, subsystems, and defined portions of SoC programs.
Build and maintain reusable testbench components, tests, assertions, checkers, scoreboards, and coverage models.
Drive verification closure through stimulus development, coverage analysis, and signoff tracking.
Analyze logs and waveforms, resolve complex testbench and design failures, and coordinate issue resolution with RTL, architecture, firmware, and verification engineers.
Improve verification automation, reuse, debug efficiency, and development methods while leading technical reviews and guiding other engineers.
Requirements
Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 2–4 years of relevant industry experience, or a related bachelor’s degree with 4–5 years of relevant industry experience.
Demonstrated mastery of multiple aspects of SoC design verification and recognized technical contributions within a work group.
Advanced experience with SystemVerilog, UVM, constrained-random verification, functional coverage, and SystemVerilog assertions.
Experience with at least one scripting language, including Python, Tcl/Tk, Perl, or Shell.
Experience running EDA verification and debug tools in a UNIX design environment.
Ability to conduct project-based work independently with limited input, apply specialized knowledge to complex technical problems, and improve processes and methods.
Ability to train, guide, and collaborate with engineers in a technical team.
Nice to have
Power-aware verification using UPF, including isolation, retention, and power-state transitions.
Experience with CPU architectures such as RISC-V, Arm, or MIPS.
Experience with SoC protocols or interfaces such as AXI, AHB, APB, SPI, I²C, or UART.
Experience with UVM RAL, SystemRDL, IP-XACT, or register-model generation flows.
Experience with formal verification, gate-level simulation, emulation, FPGA prototyping, or hardware/software co-verification.
C or C++ experience related to embedded software, test development, or reference models.
Culture & Benefits
Full-time employment in a semiconductor design and manufacturing environment.
Work safely and responsibly while supporting Environmental, Health, Safety & Security requirements and programs.
Employment is subject to applicable pre-employment conditions, laws, and regulations.
hirify.global is committed to equal opportunity and workplace diversity.
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