aipythonverilogsystemverilogrtldigital logicsilicon photonicsasic designmixed signal simulation
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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$164к-222к/год
$200к$220кмедиана$260к
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Крутая вакансия
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Чётко очерченная senior-роль в проектировании чипов у продуктовой компании в сфере фотоники для ИИ даёт редкую возможность влиять на сложную технологию; требования и условия описаны достаточно конкретно.
Ограничения по экспорту
Современный стек
Инфраструктура для ИИ
Понятная зона ответственности
Поддержка развития
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Sr/Staff Digital Design Engineer (AI/ASIC): Develop RTL modules and high-performance, low-power digital designs for next-generation AI accelerators and optical computing systems with an accent on SystemVerilog, DFT considerations, and mixed-signal simulation. Focus on integrating silicon photonic communication and compute technology, debugging complex logic, and coordinating implementation across architecture, verification, physical design, photonic, analog, and software teams.
Location: Mountain View, CA; other locations: Boston, MA and Toronto, ON. Flexible hybrid workplace model.
Salary: $164,000–$222,000 USD base salary. Total compensation also includes equity grants and other rewards.
Company
hirify.global develops AI data center infrastructure and photonics technology, including 3D-stacked photonics engines for extreme-scale AI and HPC workloads.
What you will do
Develop SystemVerilog RTL modules with DFT considerations for ASIC and IC development.
Debug complex logic and mixed-signal simulations.
Integrate silicon photonic communication and compute technology into digital accelerator designs.
Collaborate with architecture, design verification, physical design, photonic, analog, and software teams to deliver high-performance, low-power designs in advanced technology nodes.
Create module specifications and documentation covering functionality and timing.
Manage RTL implementation, schedules, and technical risks to deliver functionally correct, performant designs.
Requirements
Bachelor’s degree in Electrical or Computer Engineering or a related field.
At least 5 years of ASIC design or similar high-speed chip design experience, including multiple successful tape-outs.
Proficiency in SystemVerilog or Verilog for digital logic design.
Experience debugging complex logic and mixed-signal simulations with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, Questa, or equivalent mixed-signal co-simulation environments.
Track record of delivering high-performance, low-power digital designs in advanced semiconductor process nodes.
Capacity to comply with federally mandated U.S. export control requirements.
Nice to have
Master’s degree in Electrical or Computer Engineering or a related field.
Experience with communication protocols such as PCIe.
Knowledge of processor design, accelerators, and/or memory hierarchies.
Exposure to silicon photonics, optical compute/interconnect architectures, or electro-optic interface integration.
Scripting skills in Python, Perl, Tcl, or Bash for automating simulation and design workflows.
Experience interfacing digital logic directly with analog mixed-signal IP such as SerDes, ADCs/DACs, or optical transceivers.
Culture & Benefits
Flexible hybrid workplace model.
Medical, dental, and vision coverage.
Retirement savings matching, life insurance, disability coverage, and generous vacation, sick leave, and public holidays.
Paid family leave, commuter benefits, and training and development.
Equity grants for full-time employees; benefits eligibility may vary by employment status and location.
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