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8 дней назад

Design Verification Engineer Intern (Summer 2027) (CPU Verification)

20 - 40$
Формат работы
onsite
Тип работы
fulltime
Грейд
trainee
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Design Verification Engineer Intern (Summer 2027) (CPU Verification) (SystemVerilog/UVM): Verifying CPU cores and related subsystems with an accent on microarchitectural specifications, constrained-random testing, coverage-driven verification, and regression automation. Focus on developing testbenches and test cases, closing functional and code coverage gaps, and analyzing CPU functionality, performance, and modeling.

Location: Richardson, Texas, United States; the role description specifies the CPU verification team in Plano, Texas. Onsite internship.

Expected salary: $20.00–$40.00 per hour; the exact salary depends on qualifications, experience, and location.

Company

hirify.global manufactures essential semiconductors for high-growth markets, including AI-enabled applications, with a focus on power efficiency, performance, security, longevity, and sustainability.

What you will do

  • Perform functional verification of CPU cores and related subsystems.
  • Interpret microarchitectural specifications and develop verification strategies and plans.
  • Create testbenches and directed or constrained-random test cases in SystemVerilog, C, and Assembly.
  • Use UVM-based environments for coverage-driven verification.
  • Analyze coverage reports and help close functional and code coverage gaps.
  • Automate regression and verification flows with Python, Perl, or Shell while collaborating with engineers and architects.

Requirements

  • Be at least a sophomore at application time and actively pursue a Bachelor's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science, or a related field through an accredited program during the internship.
  • Maintain an overall GPA of at least 3.0 and good academic standing.
  • English fluency in written and verbal communication is required.
  • Be able to work at least 40 hours per week during the internship.
  • Have coursework or project experience with SystemVerilog, UVM, or constrained-random verification.
  • Have familiarity with CPU architectures such as RISC-V, ARM, or MIPS, plus a basic understanding of cache and coherency concepts.
  • Have scripting experience with Python, Perl, or Shell.
  • Demonstrate analytical, problem-solving, and technical communication skills, as well as self-motivation and collaboration.

Nice to have

  • Prior related internship or co-op experience.
  • Leadership experience in the workplace, school projects, or competitions.
  • Interest in using AI tools and emerging technologies to improve productivity, workflows, and decision-making.
  • Project management, innovation, execution, ambiguity navigation, planning, and organizational skills.
  • Exposure to RISC-V architecture.
  • Knowledge of AXI, ACE, or CHI interconnect protocols.
  • Experience with FPGA prototyping or emulation platforms.

Culture & Benefits

  • Paid full-time summer internship with a minimum commitment of 40 hours per week.
  • One-on-one mentorship and work assignments focused on professional growth.
  • Professional development opportunities and networking with executives.
  • Collaboration with experienced CPU architects, designers, and verification engineers.
  • Work must be performed safely and in accordance with Environmental, Health, Safety & Security requirements.

Hiring process

  • An offer is conditional on successful completion of applicable pre-employment conditions and compliance with applicable laws and regulations.
  • Reasonable-accommodation requests for the employment process must be sent to the specified accommodations email with the nature of the request and contact information.

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