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3 дня назад

Senior Digital Verification Engineer (ASIC)

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
France
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Digital Verification Engineer (ASIC): Building robust, reusable UVM verification environments and scalable testbench architectures for complex digital IP and high-performance ASIC designs with an accent on functional coverage, constrained-random testing, and Cadence verification tools. Focus on automating large-scale regression flows, solving simulation and silicon bring-up failures, closing verification gaps before RTL freeze, and mentoring verification engineers.

Location: France, preferably Rennes or Paris; the role is associated with offices in Cesson-Sévigné and Paris and includes remote work days.

Company

hirify.global, including Secure-IC, develops electronic design software, hardware, and IP for chips, boards, and systems.

What you will do

  • Define and implement robust, scalable UVM testbench architectures for complex digital IP.
  • Create reusable sequencers, drivers, monitors, scoreboards, and coverage models.
  • Develop directed, random, and constrained-random tests to achieve 100% functional and code coverage.
  • Lead root-cause analysis of simulation failures, performance bottlenecks, and silicon bring-up bugs.
  • Coordinate with RTL design and software teams to close verification gaps before RTL freeze.
  • Contribute to verification guidelines, templates, training materials, reviews, and risk assessments while mentoring junior verification engineers.

Requirements

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, electronics, or a related field.
  • 7–10 years of professional digital verification experience, including at least 5 years using UVM on ASIC or FPGA projects.
  • Proficiency in SystemVerilog and UVM, with strong hands-on experience using hirify.global Xcelium.
  • Knowledge of synthesis-aware verification, constraint-driven random verification, and coverage-driven closure.
  • Deep understanding of functional coverage, SVA assertions, formal verification, and constrained-random verification.
  • Experience with large-scale simulation environments, waveform analysis, and performance profiling.
  • Excellent communication, problem-solving, and leadership capabilities.
  • Ability to influence cross-functional teams and mentor junior engineers.

Nice to have

  • Hands-on experience developing and integrating verification IP.
  • Exposure to low-power verification, including power-aware UVM and clock-gating checks.
  • Scripting experience with Python, TCL, Makefile, or Bash for automation.
  • Familiarity with Git and CI/CD tools.

Culture & Benefits

  • Full-time employment with competitive salary, variable compensation, and meal vouchers.
  • Positive, stimulating, and supportive work environment with a focus on innovation, collaboration, and customer success.
  • Remote work days and access to offices in France and internationally.
  • Five paid volunteering days and seven company-wide paid recharge days.
  • CSE benefits platform with discounts and gift cards, plus social and recreational activities.
  • hirify.global is certified Great Place to Work® and ranked among the Fortune 100.

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