Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Текст:
Hirify AI/Оригинал
TL;DR
Head - SoC Physical Design Manager (Mixed-Signal ICs): Leading the physical design organization responsible for implementing and signing off complex mixed-signal SoCs from physical architecture and floorplanning through place and route, timing closure, physical verification, and tape-out with an accent on power management, signal integrity, reliability, and PPA optimization. Focus on building engineering capability, solving advanced timing, congestion, power, and physical-verification challenges, and standardizing EDA methodologies across NXP.
Location: Sophia-Antipolis (Valbonne), France; other location: Gratkorn
Company
hirify.global develops products enabling trusted physical AI and advanced semiconductor solutions.
What you will do
Lead, develop, and grow the Physical Design, STA, and signoff organization.
Own physical design strategy and execution for complex IC and mixed-signal SoC developments from physical architecture and floorplanning through tape-out.
Direct floorplanning, partitioning, power planning, placement, clock-tree implementation, routing, physical optimization, timing closure, and signoff.
Lead power-management implementation, power integrity, reliability, mixed-signal physical integration, and physical verification.
Partner with architecture, RTL, front-end, analog, packaging, EDA, technology, library, and IP teams to influence design decisions and resolve complex technical challenges.
Drive cross-NXP best practices, methodology standardization, automation, flow reuse, and adoption of improved implementation technologies.
Requirements
Significant experience in advanced IC/SoC Physical Design, including multiple successful tape-outs and ramp of high-volume products.
Deep expertise in Place & Route, STA, timing closure, packaging, physical signoff, IR-drop, electromigration, signal integrity, power integrity, and reliability.
Experience with low-power designs involving multiple voltage domains, power gating, level shifting, isolation, and always-on domains.
Strong understanding of interactions between architecture, RTL, synthesis, DFT, Physical Design, analog design, packaging, and silicon validation.
Experience improving and industrializing EDA methodologies, automation, and design flows.
Proven experience leading and developing engineering teams, mentoring technical experts, and building future technical and organizational leaders.
Experience collaborating across multiple organizations, sites, or business groups and influencing decisions beyond the direct reporting organization.
Strong communication skills, with the ability to translate complex engineering issues into clear technical and program decisions.
Nice to have
Experience in the Physical Design of secure products.
Culture & Benefits
Full-time leadership role with responsibility for building a strong Physical Design organization.
Culture focused on technical excellence, collaboration, ownership, accountability, and continuous improvement.
Opportunity to develop engineering talent and establish common methodologies and best practices across NXP.
Cross-organizational collaboration with Physical Design teams and technical communities across NXP.
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