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8 дней назад

Senior ASIC Verification Engineer

158 500 - 321 000$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior ASIC Verification Engineer (SystemVerilog/UVM): Developing and verifying high-speed networking ASICs and SoC modules from test planning through coverage closure with an accent on block-level and subsystem verification, constrained-random testing, assertions, and waveform debugging. Focus on building advanced UVM environments, analyzing complex simulations, and resolving functional issues across cross-functional silicon development teams.

Location: Hybrid role based in Sunnyvale, California, with an expectation of working in the office 2 days per week

Salary: USD 158,500–321,000 annual base salary in California; variable incentives may also be offered.

Company

hirify.global is a global edge-to-cloud company developing networking technologies, including routers, switches, and high-speed networking silicon.

What you will do

  • Own and drive block-level or subsystem verification from test-plan creation through comprehensive coverage closure.
  • Develop, enhance, and maintain UVM environments, including agents, sequences, scoreboards, virtual sequences, and register models.
  • Perform constraint-driven random testing, debug complex SoC designs, and meet functional coverage and assertion goals.
  • Analyze simulations with Cadence Xcelium, Synopsys VCS, and Mentor Questa, including waveform debugging.
  • Collaborate with cross-functional teams to identify and resolve issues and deliver high-quality ASIC/SoC designs.

Requirements

  • 10+ years of ASIC/SoC verification experience, including ownership from test planning through coverage closure.
  • Strong expertise in SystemVerilog and UVM, including developing verification environments from scratch.
  • Deep understanding of randomization, constraints, functional coverage, and SVA assertions.
  • Hands-on experience with test planning, coverage analysis, and debugging complex SoC designs.
  • Proficiency with industry-standard simulation tools such as Cadence Xcelium, Synopsys VCS, and Mentor Questa, plus waveform debugging.

Nice to have

  • Experience verifying networking ASICs or router datapath/control blocks, including packet processing, forwarding engines, or fabric interfaces.
  • Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
  • Exposure to emulation, hardware acceleration, or traffic-model integration.
  • Knowledge of coverage analytics, regression dashboards, continuous-integration flows such as Jenkins, low-power UPF, or formal verification.
  • Experience with FullChip verification, post-silicon bring-up and debug, and emulation debug flows.

Culture & Benefits

  • Work in an inclusive, collaborative environment focused on open communication, empowerment, innovation, teamwork, and customer success.
  • Access comprehensive health and wellbeing benefits for employees and their loved ones.
  • Receive personal and professional development programs supporting career growth and knowledge expertise.
  • Accommodation support is available during the application or interview process for applicants with disabilities.

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