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13 дней назад

ASIC Design Engineer (Physical Design)

61 900 - 99 000$
Формат работы
onsite
Тип работы
fulltime
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
ASIC Design Engineer (Physical Design): Developing and implementing high-performance CMOS ASICs for AI, cellular, networking, computing, and storage products with an accent on advanced 3 nm and smaller process nodes, physical implementation, and design verification. Focus on floorplanning, placement, clock tree synthesis, routing, timing closure, power and physical verification, and delivering designs from RTL to GDSII and silicon bring-up.

Location: Fort Collins, Colorado, USA; onsite at 4380 Ziegler Road

Annual base salary: USD 61,900–99,000

Company

hirify.global develops custom CMOS ASICs for AI, cellular, networking, computing, and storage products.

What you will do

  • Implement large-scale, multi-hundred-million-gate ASICs through physical design.
  • Support floorplanning, placement, clock tree synthesis, routing, timing closure, and DRC/LVS physical verification.
  • Collaborate on block-level integration, timing analysis, design signoff, and technical design reviews.
  • Use commercial and in-house EDA tools for implementation and verification.
  • Improve design flows, automation, and deep sub-micron methodologies.
  • Contribute to power planning, IR/EM checks, post-route optimization, and the ASIC cycle from RTL to GDSII and silicon bring-up.

Requirements

  • Bachelor’s or master’s degree in Electrical or Computer Engineering.
  • Solid understanding of VLSI design, CMOS logic, and digital circuit fundamentals.
  • Familiarity with ASIC physical design, including placement, routing, and timing.
  • Strong analytical and debugging skills, with the ability to learn new tools and flows quickly.
  • Proficiency in UNIX/Linux environments and working knowledge of TCL.
  • Excellent communication, collaboration, and problem-solving abilities; ability to work with cross-functional and global teams.
  • Engineering judgment, ownership, accountability, attention to detail, and motivation to learn in a fast-paced R&D environment.

Nice to have

  • Familiarity with Python or Perl.
  • Exposure to Cadence Innovus, Synopsys ICC2, or PrimeTime.

Culture & Benefits

  • Work with a cross-functional custom silicon design team on advanced 3 nm and smaller process nodes operating above 1 GHz.
  • Collaborate closely with senior engineers across multiple disciplines and support customer and internal stakeholder discussions.
  • Eligible for a discretionary annual bonus, new-hire equity grant, and annual equity awards, subject to plan documents and award agreements.
  • Benefits include medical, dental and vision plans, 401(k) with company matching, ESPP, EAP, paid holidays, paid sick leave, vacation, and applicable family and other leave.

Hiring process

  • First-time users must create a candidate login account before applying; existing candidates must sign in before applying.
  • Applicants outside the USA should provide a home address for future correspondence.

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