Senior Engineer II - Layout (Semiconductor)

Location: San Jose, California, United States; onsite role with 0%–25% travel, usual business hours.

Annual base salary: $70,304–$205,000, plus restricted stock units and quarterly bonus payments.

Company

hirify.global is a global semiconductor technology company developing products and solutions that power technologies worldwide.

What you will do

• Define and execute complex layout architectures, floorplans, device structures, interconnect, power distribution, matching, shielding, extraction, and verification strategies.
• Integrate circuit, technology, performance, power, area, reliability, manufacturability, design-rule, and schedule requirements.
• Resolve critical layout, connectivity, parasitic, matching, coupling, electromigration, physical-verification, integration, and tapeout-readiness issues through root-cause analysis.
• Evaluate evidence, uncertainty, risks, dependencies, waivers, and alternatives and communicate decision-ready recommendations.
• Coordinate cross-functional layout decisions and closure with circuit design, physical design, verification, technology, CAD, product, test, manufacturing, quality, reliability, and leadership teams.
• Establish reusable layout, automation, verification, extraction, design-rule, and release practices and review layouts, reports, waivers, defects, and release evidence.

Requirements

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a related field, with 7.5–10 years of relevant semiconductor experience, or closely related equivalent experience.
• Relevant experience in semiconductor layout, custom physical design, analog, digital, mixed-signal, memory, IO, ASIC, SoC layout, floorplanning, device placement, routing, extraction, or physical verification.
• Analytical thinking, semiconductor-layout judgment, geometric and spatial reasoning, structured problem solving, verification discipline, root-cause analysis, technical documentation, and evidence-based communication.
• Ability to work with complex design rules, schematics, devices, interconnect, parasitics, reliability, manufacturing, and signoff information.
• Effective teamwork, cross-functional collaboration, quality focus, employment stability, sustained accountability, integrity, and accuracy in representing qualifications, experience, and credentials.

Nice to have

• Experience with custom, analog, digital, mixed-signal, memory, IO, pad, RF, ASIC, or SoC layout.
• Experience with floorplanning, device placement, routing, matching, shielding, power distribution, extraction, DRC, LVS, ERC, antenna, density, reliability, or physical-verification closure.
• Experience with layout and physical-verification tools, scripting, automation, process-design kits, advanced process nodes, or design-for-manufacturing methods.
• Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a related field.

Culture & Benefits

• Full-time employment in a culture emphasizing trust, empowerment, respect, diversity, communication, employee development, and community.
• Health benefits begin on day one, with retirement savings plans and an employee stock purchase plan featuring a two-year lookback.
• Compensation includes base pay, restricted stock units, and quarterly bonus payments.
• Work is primarily indoors with approximately 70% sitting, 15% standing, and 15% walking; the role involves working independently and with others.

Hiring process

• Applications from recruitment agencies are not accepted unless solicited; unsolicited agency resumes should not be forwarded.