Назад
Company hidden
7 часов назад

ASIC Architect (AI)

160 000 - 280 000$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
ASIC Architect (AI): Defining and guiding the development of high-performance ASICs for AI accelerators, networking, and datacenter computing workloads with an accent on architectural specifications, performance modeling, and power, performance, and area trade-offs. Focus on designing interconnect and I/O architectures, advanced power management, cross-functional silicon implementation, and mentoring engineers.

Location: Hybrid in Palo Alto, United States

Target base salary: $160,000–$280,000 per year, plus meaningful equity, benefits, and 401(k).

Company

hirify.global is a startup building foundational technology for performance, scalability, and resiliency challenges in large-scale AI data center clusters.

What you will do

  • Define architecture for IP blocks, subsystems, and full SoC integration for AI accelerators, networking, and datacenter computing workloads.
  • Lead Architectural Design Specifications and Micro-architecture Specifications for complex ASICs, including Ethernet, PCIe, UCIe, and high-speed interconnect fabric.
  • Develop performance models with SystemC/TLM, C++, or Python to analyze workloads and validate architectural assumptions.
  • Optimize chip- and block-level designs against power, performance, and area goals, including DVFS, power domains, and clock gating.
  • Collaborate with RTL design, verification, physical design, firmware, and software teams; lead trade-off studies and design reviews.
  • Mentor junior engineers and provide technical leadership.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • 7+ years of experience in ASIC architecture, micro-architecture, or high-level design.
  • Strong proficiency in SystemVerilog/Verilog and C/C++ or SystemC for modeling.
  • Deep knowledge of computer architecture, including CPU/GPU cores, caches, fabric, and memory hierarchies.
  • Experience with industry-standard protocols such as Ethernet, PCIe, or UAL.
  • Familiarity with EDA tools such as Synopsys Design Compiler, Cadence Genus, or similar, plus performance modeling and analysis tools.

Nice to have

  • Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
  • Experience designing AI/ML accelerators or high-performance networking silicon.
  • Experience shipping high-performance silicon from concept to tape-out.
  • Familiarity with pre-silicon emulation platforms.
  • Python, Tcl, or Perl scripting for automation.
  • Excellent communication, proactive problem-solving, independent execution, leadership, and mentorship skills.

Culture & Benefits

  • Work in a hybrid environment across remote and on-site locations in the United States and Canada.
  • Collaborate with experienced builders and operators with a strong sense of unity and shared responsibility.
  • Culture emphasizes trust, integrity, respect, accountability, fairness, growth, and meaningful technical work.
  • Benefits include meaningful equity, benefits, and a 401(k).

Hiring process

  • Applications from agencies or search firms are not accepted; do not forward candidate profiles through the careers page, email, LinkedIn messages, or directly to company employees.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →