Staff Logic Design Engineer (FPGA)

Location: Milpitas, California, United States; onsite role. Travel is minimal, under 10%, for lab collaboration or customer support.

Salary: $141,900–$189,200 per year.

Company

hirify.global, part of Teledyne Technologies, develops high-reliability technologies and Teledyne LeCroy provides protocol analysis and test solutions for high-speed serial data communications.

What you will do

• Architect and implement synthesizable Verilog/SystemVerilog RTL for protocol capture, packet parsing, timestamping, buffering, and control logic.
• Develop FPGA systems on Xilinx Versal and Intel Agilex, including synthesis, place-and-route, timing closure, resource optimization, PCIe IP, DMA engines, and protocol decoders.
• Build SystemVerilog/UVM testbenches and perform simulation, waveform analysis, functional coverage, and design debugging.
• Integrate and validate protocol analyzer platforms with hardware, firmware, and software teams.
• Support laboratory debugging with logic analyzers, oscilloscopes, ILA, SignalTap, and other in-system FPGA tools.
• Create design specifications, interface documents, and verification plans; participate in design reviews and improve design practices.

Requirements

• BS degree in electrical engineering, computer science, or computer engineering required; an MS in electrical engineering is a plus.
• 7+ years of experience in digital logic design for FPGA or ASIC.
• Strong proficiency in Verilog/SystemVerilog RTL design.
• Experience with one or more of PCIe, CXL, NVMe, USB, SAS, or SATA; PCIe Gen4/Gen5/Gen6 experience and familiarity with TLP, DLLP, and PHY-layer concepts are required.
• Experience with monitoring and/or test-and-measurement tools.
• Hands-on experience with FPGA toolchains such as Vivado or Quartus and timing closure.
• Knowledge of UVM, assertions, and simulation/debug tools including ModelSim or Vivado Simulator.
• Solid understanding of CDC, clock-domain design, and reset strategies.

Nice to have

• Experience with protocol analyzers, packet capture, and timestamping logic.
• Familiarity with AXI interconnects, memory controllers, and high-speed buffering.
• Exposure to SERDES, PCIe IP integration, and link-training/debug.
• Python or Tcl scripting for automation and test infrastructure.
• Experience with hardware/software co-design, register maps, and embedded firmware interaction.
• Prior work in test and measurement or semiconductor validation environments.

Culture & Benefits

• Collaborative, fast-paced, and innovation-driven team environment.
• Work focuses on high-speed protocol analysis and test-and-measurement products for data-center, AI/ML, storage, and networking technologies.
• Minimal travel, under 10%, for lab collaboration or customer support.
• Employees must comply with applicable laws, regulations, rules, and regulatory orders, and the employer maintains an equal-opportunity policy.