Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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$151к-226к/год
$170к$190кмедиана$190к
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Крутая вакансия
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Чётко очерченная ведущая роль в крупной полупроводниковой компании с ответственностью за передовые потоки проектирования analog, mixed-signal и silicon photonics; требования экспортного контроля ограничивают доступ к позиции.
Экспортный контроль
Современные EDA-инструменты
Понятная зона ответственности
Фотоника для чипов
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Principal Analog/Mixed Signal CAD Engineer (Silicon Photonics): Developing and supporting automated analog and mixed-signal CAD flows, parasitic extraction, physical verification, and custom automation tools across advanced FinFET, BiCMOS, SiGe, and SiPho technologies with an accent on Cadence, Synopsys, and Siemens design environments. Focus on architecting post-layout and EMIR flows, validating foundry PDKs, debugging complex design infrastructure, and building Python, TCL, Shell, and SKILL-based productivity tools.
Location: Santa Clara, California, United States
Expected base pay: $150,680–$225,700 per annum
Company
hirify.global develops semiconductor solutions for enterprise, cloud and AI, and carrier data infrastructure.
What you will do
Architect and support automated analog and mixed-signal design flows used across design teams.
Build and maintain custom tools, PCells, Pycells, GUI utilities, and automation tools in Cadence Virtuoso, Synopsys OptoCompiler, and Siemens Calibre environments.
Install, validate, and support foundry PDKs.
Set up and maintain physical verification and parasitic extraction flows, including post-layout processes.
Partner with analog designers and EDA vendors to troubleshoot complex design-flow challenges.
Help define company-wide CAD infrastructure and best practices for analog, mixed-signal, and silicon photonics development.
Requirements
BSEE with 10–15 years of professional experience, or MS/PhD in Electrical Engineering with 5–10 years of industry experience.
Experience building and maintaining analog/mixed-signal design flows for advanced FinFET, BiCMOS, SiGe, and SiPho technologies.
Hands-on experience with Cadence Virtuoso Studio, Synopsys OptoCompiler, and Siemens Calibre.
Understanding of schematic capture, simulation, parasitic extraction, post-layout verification, and EMIR.
Programming or scripting experience in Python, TCL, Shell, and SKILL.
Experience developing custom CAD automation or verification frameworks.
Excellent communication skills and effective cross-functional collaboration.
Applicants must be eligible to access export-controlled information under applicable U.S. export control laws; some applicants may require an export license review.
Nice to have
Familiarity with silicon photonics design flows.
Culture & Benefits
Full-time employment with base pay, bonus and equity plan eligibility.
Benefits support financial well-being, family support, mental and physical health, and recognition.
Benefits include an employee stock purchase plan with a two-year lookback and family support programs.
AI tools, transcription apps, automated answer generators, and automated note-taking bots are prohibited during interviews; violating this requirement may result in disqualification.
Hiring process
Applicants requiring reasonable accommodation during selection should contact the hirify.global HR Helpdesk.
Interview responses must be provided independently without unauthorized AI assistance.
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