aiperformance modelingasicsocdmasystem simulationhbmmemory architecturesilicon architectureon die interconnect
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
$200к-320к/год
$160к$190кмедиана$190к
По похожим ролям (50) ~ $190к/год
На СНГ рынке: $2.5к/мес ($1.9к - $3.1к)
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Крутая вакансия
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В Company hidden предстоит отвечать за важную архитектуру AI-ускорителей на нескольких поколениях чипов; задачи подробно описаны и охватывают значимую техническую область.
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Высокий уровеньШирокая ответственностьАктуальная областьПакет льгот
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
AI/ML Silicon Accelerator Memory Architect (AI/ML silicon architecture): Defining end-to-end memory and data transport architectures for AI/ML accelerators with an accent on HBM, memory controllers, on-die interconnects, DMA engines, and scratchpad hierarchies. Focus on modeling latency, bandwidth, utilization, scalability, and pJ/bit trade-offs across multiple silicon generations.
Location: San Jose, California, United States
Annual base salary: USD 200,000–320,000
Company
hirify.global develops semiconductor and silicon technologies, including AI/ML accelerator architectures.
What you will do
Define multi-generation memory and data transport architectures for AI/ML accelerators.
Architect memory controllers, cache and scratchpad microarchitecture, scheduling, address mapping, and QoS across compute, DMA, and host traffic.
Own on-die interconnect topology, flow control, deadlock avoidance, mixed-traffic QoS, DMA, gather/scatter, layout-transform, and multicast engines.
Build analytical and simulation-based models to quantify performance, power, area, latency, throughput, utilization, and scalability trade-offs.
Co-architect solutions with internal teams and external memory and IP vendors across multiple silicon generations.
Requirements
18+ years of ASIC/SoC architecture experience focused on memory systems and data movement for HPC or AI.
MSEE, MSCE, or PhD in EE, CE, CS, or a related field, or equivalent demonstrated architectural impact.
Deep knowledge of HBM, DDR, LPDDR, GDDR, memory controller architecture, cache coherency, memory consistency models, tiered memory, and pooled memory.
Demonstrated ownership of data movement architecture spanning on-die interconnects, DMA/copy engines, buffer hierarchies, and dataflow to compute.
Practical understanding of the latency, area, and power costs of NVLink, UALink, RDMA, ARM CHI, UCIe, and PCIe.
Strong performance modeling and system-level simulation experience, with first-principles command of latency, throughput, utilization, and scalability.
Culture & Benefits
Full-time employment with medical, dental, and vision plans.
401(k) participation with company matching, ESPP, and EAP.
Company-paid holidays, paid sick leave, vacation time, and applicable paid family and other leaves.
Eligibility for a discretionary annual bonus, new-hire equity grant, and annual equity awards, subject to plan documents and award agreements.
The role is associated with a United States workplace in San Jose, California.
Hiring process
First-time applicants must create a candidate login account before applying; existing candidates must sign in before applying.
Applicants located outside the USA should provide a home address for future correspondence.
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