Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Company hidden предлагает заметную техническую ответственность в новом R&D-центре, работающем над AI-инфраструктурой; при этом уровень Principal выглядит спорно рядом с минимальным требованием всего в три года опыта.
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Уровень под вопросомАктуальный стекИнфраструктура для AIОтветственность с начала
Оценка от Hirify AI
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Principal Physical Design CAD Engineer (GenAI) (Semiconductor/AI Infrastructure): Developing and improving CAD flows, automation infrastructure, and parasitic extraction methodologies for complex semiconductor chips with an accent on Synopsys Fusion Compiler, physical design implementation, and GenAI-based engineering tools. Focus on analyzing timing, power, congestion, QoR, design-rule issues, and building robust automation from synthesis through signoff readiness.
Location: Tel Aviv-Yafo, Tel Aviv District, Israel; other location: Israel
Company
hirify.global develops rack-scale AI infrastructure and semiconductor connectivity solutions based on CXL, Ethernet, NVLink, PCIe, and UALink technologies, supported by its COSMOS software suite.
What you will do
Develop, maintain, and improve physical design CAD flows and methodologies using industry-standard EDA tools.
Build automation infrastructure for implementation, analysis, reporting, debugging, and large-scale design flows.
Support synthesis, floorplanning, placement, clock-tree synthesis, routing, timing closure, power optimization, physical verification, and signoff readiness.
Create scripts and utilities that improve productivity, result quality, and flow robustness.
Support and enhance Synopsys Fusion Compiler-based flows.
Explore and integrate GenAI solutions for debugging, repetitive-task automation, reporting, and engineering productivity.
Requirements
At least 3 years of hands-on experience in physical design, CAD, or implementation methodology.
Strong understanding of digital physical design, including synthesis, placement, CTS, routing, timing closure, and physical verification.
Hands-on experience with Synopsys Fusion Compiler.
Experience with Tcl and Python scripting.
Ability to develop automation around EDA tools and large-scale design flows.
Understanding of timing, power, congestion, floorplanning, and QoR analysis.
Strong debugging and problem-solving skills.
Ability to collaborate with multiple engineering teams and support complex design environments.
Motivation to learn and apply GenAI technologies in semiconductor design flows.
Nice to have
Experience with PrimeTime, StarRC, ICC2, Innovus, Voltus, RedHawk, Calibre, or similar tools.
Knowledge of STA, low-power design, UPF, EM/IR, extraction, or signoff flows.
Experience building dashboards, regression systems, flow checkers, or automated report analyzers.
Familiarity with LLMs, prompt engineering, AI agents, or GenAI-based coding and debugging tools.
Experience with Git, CI/CD, databases, or cloud-based compute environments.
Culture & Benefits
Join a strategic R&D center in Israel developing semiconductor chips for large-scale AI infrastructure.
Work as a foundational member of a new site with meaningful technical ownership.
The company encourages applications from people with diverse backgrounds and experiences, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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