Staff/Principal Physical Design STA Engineer (Semiconductor)

Location: Haifa District, Israel; other locations: Israel

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

• Execute STA flows and sign-off methodologies for high-performance chips used in demanding data center environments.
• Collaborate with Architecture, Design, DFT, and Backend teams on timing reviews and sign-off convergence.
• Develop, optimize, and manage SDC constraints across multi-scenario environments.
• Analyze cross-chip clock distribution and apply margining techniques across process corners.
• Improve design methodologies and automate sign-off using EDA tools and custom scripts.

Requirements

• B.Sc. in Electrical Engineering or Computer Engineering.
• 6+ years of hands-on STA experience at semiconductor companies, specifically with advanced process technologies.
• Deep expertise in multi-scenario STA and timing and SDC constraint development and verification at block and subsystem levels.
• Strong understanding of OCV, AOCV, and POCV margining methodologies from synthesis through final sign-off.
• Solid knowledge of physical design flows, including synthesis, P&R, and physical verification, and their interaction with timing closure.

Nice to have

• Experience developing and validating constraints with Timing Constraints Manager or TimeVision.
• Experience executing STA on complex macro-level designs and supporting full-chip timing integration.
• Strong scripting background in Tcl, Python, or Perl for timing-closure automation.

Culture & Benefits

• Join a strategic R&D center in Israel being built to develop complex semiconductor chips for AI infrastructure.
• Work in a diverse environment that encourages applications from people with varied backgrounds and experiences.