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3 дня назад

Principal DFT Engineer

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Israel
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Мэтч & Сопровод

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Описание вакансии

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TL;DR
Principal DFT Engineer (AI connectivity semiconductors): Defining and leading DFT architecture, implementation, verification, silicon bring-up, and production support for complex SoCs and chiplet-based AI connectivity solutions with an accent on Scan, MBIST, LBIST, JTAG/iJTAG, ATPG, and manufacturability. Focus on driving full-lifecycle DFT execution, building scalable automation and verification flows, and solving integration, coverage, timing, PPA, and first-pass silicon challenges.

Location: Haifa District, Israel

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and its COSMOS software suite, integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

  • Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies.
  • Lead DFT planning, specification, implementation, integration, verification, quality tracking, and sign-off across block, full-chip, and chiplet levels.
  • Drive end-to-end DFT activities from specification through tapeout, silicon bring-up, and production support.
  • Develop scalable DFT methodologies, flows, and automation frameworks to improve test quality, PPA, and turnaround time.
  • Collaborate with RTL, Physical Design, STA, and Test Engineering teams on DFT readiness, timing implications, and integration challenges.

Requirements

  • Bachelor’s degree in Electrical Engineering or a related technical field; a Master’s degree is preferred.
  • 12+ years of experience in DFT design, implementation, and verification for complex ASIC/SoC designs.
  • Experience leading DFT activities across full-chip development cycles.
  • Deep expertise in Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG.
  • Strong understanding of DFT and Physical Design flows, including timing implications and integration challenges.
  • Experience with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX, or equivalent.
  • Experience with DFT verification methodologies and coverage analysis.
  • Strong scripting skills in Tcl, Python, or Perl for automation and flow development.

Nice to have

  • Experience with advanced process nodes of 7nm and below.
  • Background in high-speed connectivity designs such as PCIe, Ethernet, CXL, or similar technologies.
  • Experience with hierarchical DFT methodologies and large multi-die or chiplet-based systems.
  • Knowledge of silicon bring-up, production test flows, and yield optimization.
  • Familiarity with STA, low-power design, and CDC as related to DFT integration.
  • Strong leadership and communication skills, including the ability to influence cross-functional teams globally.

Culture & Benefits

  • Join a strategic R&D center in Israel being established to develop complex semiconductor chips for AI infrastructure.
  • Take meaningful product ownership while helping build a local engineering organization from the ground up.
  • Work in an environment that encourages diverse ideas, backgrounds, and experiences.

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