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3 дня назад

Senior/ Staff Physical Design Engineer

Формат работы
onsite
Тип работы
fulltime
Грейд
senior/lead
Английский
b2
Страна
Israel
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Senior/ Staff Physical Design Engineer (AI semiconductor connectivity): Building and implementing complex semiconductor chips for AI infrastructure with an accent on RTL2GDS execution, macro-level physical design, and advanced-node signoff. Focus on floorplanning, complex routing, timing and physical verification, reliability analysis, and automation of EDA flows.

Location: Tel Aviv-Yafo, Israel

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

  • Join the founding Backend team in Israel and help establish local execution culture, technical standards, and methodologies.
  • Own the physical implementation journey from synthesis through floorplanning, place and route, and clock-tree synthesis.
  • Lead macro-level implementation, including floorplanning and complex routing.
  • Drive timing signoff, physical verification, EMIR reliability analysis, and logic equivalence checking.
  • Collaborate with Architecture, Design, and DFT teams on advanced process nodes and high-speed connectivity.
  • Develop scripting and automation to improve EDA workflows and engineering productivity.

Requirements

  • Bachelor's degree in Electrical Engineering or a related technical field.
  • 3+ years of hands-on Physical Design experience at semiconductor companies.
  • Expertise in the full RTL2GDS flow, including macro-level implementation, floorplanning, and complex routing.
  • Experience with advanced process technologies at 7nm and below.
  • Experience with STA, Logic Equivalence Checking, DRC, and EMIR signoff flows.
  • Proficiency in TCL or Python scripting for EDA tool flows and automation.

Nice to have

  • Full-chip implementation and integration experience.
  • Knowledge of Power and Noise analysis, including SI/PI.
  • Familiarity with DFT requirements and their impact on physical layout.
  • Experience with Synopsys Fusion Compiler, ICC2, or Cadence Innovus.
  • Background in high-speed interface designs or connectivity protocols.

Culture & Benefits

  • Opportunity to help build a new strategic R&D center and local engineering organization in Israel.
  • Meaningful product ownership over backend execution and methodologies for AI infrastructure connectivity.
  • Inclusive workplace encouraging applications from people with diverse backgrounds and experiences.

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