Staff/Principal Chip Top Physical Design Engineer (AI)

Location: Haifa District, Israel; other location: Israel

Company

hirify.global develops rack-scale AI infrastructure and semiconductor connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and software technologies.

What you will do

• Execute SoC top-level physical design and drive full-chip convergence.
• Perform floor-planning, place and route, clock tree synthesis, power and clock distribution, power integrity, timing, and physical signoff.
• Collaborate with Architecture, Design, DFT, Product, and Package teams to optimize power, performance, area, and quality of results.
• Resolve signal integrity, thermal, and power challenges in high-speed connectivity silicon.
• Drive tape-out GDS through timing, LVS, EMIR, DRC, and other signoff criteria.

Requirements

• B.Sc. or M.Sc. in Electrical Engineering.
• 5+ years of hands-on Chip Top Physical Design or Backend experience at leading semiconductor companies, including advanced process technologies of 5nm, 3nm, and below.
• Experience executing complex block- or chip-level projects with a proactive approach and excellent communication skills.
• Hands-on expertise in RTL2GDS flows, including place and route, STA, physical verification with DRC/LVS, formal verification, low-power implementation with UPF/CPF, and EMIR.
• Mastery of Synopsys Fusion Compiler or ICC2, or Cadence Innovus.
• Practical experience with complex macro/subsystem-level designs and full-chip integration.

Nice to have

• Deep understanding of power and noise analysis, including EM/IR.
• Experience integrating DFT into physical design flows.
• Background in high-speed interfaces or data center protocols.

Culture & Benefits

• Join a new strategic Israel R&D center focused on complex semiconductor chips for AI infrastructure.
• Work in a diverse environment that encourages applications from people with varied backgrounds and experiences.