Physical Design Engineer, New Grad

Location: San Jose, California, United States; other listed locations: Austin, Texas and San Jose, California

Base salary: $120,000–$150,000 USD per year

Company

hirify.global develops AI infrastructure based on its RDU reconfigurable dataflow chip and SambaRack rack-scale hardware for deploying advanced AI models.

What you will do

• Run synthesis and place-and-route flows using Cadence Genus, Innovus, and Cerebrus.
• Write TCL and Python scripts to automate and improve the RTL-to-GDS physical design flow.
• Help physical designers debug timing, congestion, and design-rule issues.
• Work with tool vendors to report bugs and test flow improvements.
• Maintain flow documentation and regression testing.

Requirements

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• Coursework or project experience in VLSI or digital IC design.
• Understanding of the RTL-to-GDS flow, including synthesis and place and route.
• Scripting experience in TCL, Perl, or Python.

Nice to have

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience with Cadence or Synopsys physical design tools.
• Familiarity with static timing analysis.
• Familiarity with physical design rules on advanced process nodes.
• Experience using AI tools such as Claude for flow development.
• Internship or tape-out experience, including class or university tape-outs.

Culture & Benefits

• Full-time US-based employment with equity and benefits.
• Medical insurance with 95% employee premium coverage and 77% dependent premium coverage.
• Health Savings Account with employer contribution, Dental, Vision, Disability, Life, AD&D, and Flexible Spending Account options.
• Well-being benefits including Headspace, Gympass+, One Medical, and counseling through an Employee Assistance Program.