Engineer II - Physical Design

Location: AZ - Chandler, United States of America; onsite

Company

hirify.global develops semiconductor technology and products through a global organization of approximately 17,000 employees.

What you will do

• Develop and maintain ASIC or SoC physical-design blocks, constraints, scripts, flows, and design data.
• Translate architecture and RTL requirements into synthesis, floorplanning, placement, clocking, routing, timing, power, and verification objectives.
• Execute implementation, regression, extraction, timing, power, physical-verification, and applicable signoff checks.
• Troubleshoot flow, constraint, timing, congestion, power, signal-integrity, physical-verification, and integration issues.
• Analyze reports, logs, defects, risks, dependencies, and tradeoffs; recommend corrective actions.
• Coordinate deliverables and documentation across architecture, RTL, verification, DFT, analog, package, CAD, product, test, manufacturing, and leadership teams.

Requirements

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field, with 2.5–5 years of relevant experience in ASIC or SoC physical design, synthesis, floorplanning, placement, clock-tree synthesis, routing, extraction, static timing analysis, power integrity, physical verification, EDA flows, or closely related equivalent experience.
• Analytical thinking, semiconductor physical-design judgment, structured problem solving, timing and power analysis, debugging, and root-cause analysis.
• Technical documentation, evidence-based communication, cross-functional collaboration, and quality focus.
• Ability to work with complex architecture, RTL, constraints, libraries, layout, timing, power, physical-verification, reliability, and manufacturing information.
• Employment stability, reliability, sustained accountability, effective teamwork, integrity, and accuracy in representing qualifications, experience, and credentials.

Nice to have

• Experience with ASIC or SoC physical design, synthesis, floorplanning, placement, clock-tree synthesis, routing, extraction, static timing analysis, power integrity, or physical verification.
• Experience with EDA tools, scripting, automation, design constraints, low-power implementation, variation analysis, design-for-test, advanced process nodes, or tapeout flows.
• Experience resolving timing, congestion, power, signal-integrity, physical-verification, integration, reliability, or manufacturability issues.
• Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field.

Culture & Benefits

• Full-time employment in Chandler, Arizona.
• Culture emphasizing trust, empowerment, respect, diversity, communication, employee development, and values-based decision making.
• Leadership development programs and career-growth opportunities.
• Equal opportunity employment; unsolicited recruitment-agency resumes are not accepted.