Назад
Company hidden
14 часов назад

Design Automation Engineer (TFM/EDA)

137 610 - 265 870$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Design Automation Engineer (TFM/EDA) (Semiconductor Design Automation): Installing, maintaining, and automating semiconductor design environments, including PDKs, EDA tools, licenses, and workflows, with an accent on front-end and back-end tool integration, physical design methodologies, and infrastructure support. Focus on resolving tool issues through TapeOut, debugging design flows, provisioning compute capacity, and improving scalable automation across design teams.

Location: Hybrid role with on-site and off-site work at assigned Intel sites in Folsom, California; Phoenix, Arizona; Santa Clara, California; or Hillsboro, Oregon. US Citizenship is required, and the role operates in the United States.

Annual salary: $137,610–$265,870 USD.

Company

Intel Foundry develops semiconductor manufacturing and design solutions for Intel engineering teams and next-generation products.

What you will do

  • Install, maintain, and support design automation scripts, front-end and back-end EDA tools, workflows, and licenses.
  • Resolve tool and methodology issues across the design path to TapeOut.
  • Develop automation for installing and optimizing PDKs, EDA tools, licenses, and design environments.
  • Integrate new tools and methods into existing workflows and improve scalability and adoption across design teams.
  • Collaborate with EDA providers, PDK and library experts, flow development teams, product designers, and engineering compute teams.
  • Provide training and documentation for design ramp-up activities and troubleshoot compute capacity issues.

Requirements

  • US Citizenship and ability to obtain a US Government Security Clearance TS/SCI.
  • Bachelor’s degree in a relevant field with 6+ years of hands-on infrastructure and DevOps experience, or a Master’s degree with 4+ years, or a PhD with 2+ years.
  • Experience with front-end and back-end EDA tools, flows, and methodologies, including debugging and problem-solving.
  • Knowledge of physical design optimization and TFM tools, flows, and methodologies.
  • Experience with Tcl, Perl, and Python scripting, with familiarity with Verilog and VHDL.
  • Expertise in Linux-based environments, including bash and tcsh.

Nice to have

  • Hands-on experience installing industry-standard front-end and back-end EDA tools.
  • Experience installing foundry PDKs and flows, including Cheetah.
  • Experience with debugging and design automation.

Culture & Benefits

  • Hybrid work model combining on-site work at an assigned Intel site with off-site work.
  • Health, retirement, and vacation benefits.
  • Competitive pay and stock bonuses.
  • Collaborative environment focused on semiconductor innovation and professional growth.
  • Full-time experienced-hire position on Shift 1 in the United States.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →