FPGA Development Tools Engineer

Location: Penang 15, Penang, Malaysia; Shift 1 (Malaysia)

Company

hirify.global develops FPGA IP, simulation models, and tooling within the Quartus Prime ecosystem.

What you will do

• Define technical direction for FPGA IP and simulation models, and lead design reviews, architecture discussions, and validation strategies.
• Design and implement FPGA IP using RTL, SystemVerilog, and VHDL, and develop behavioral and cycle-accurate simulation models.
• Define verification methodologies covering SystemVerilog, assertion-based verification, testbench architecture, coverage, and regression systems.
• Lead root-cause analysis and debugging across simulation, fitter, timing analysis, compilation, and timing closure.
• Improve tool usability, debuggability, engineering productivity, automation frameworks, and regression infrastructure, including Python, Tcl, and applicable AI-assisted workflows.
• Mentor engineers in debugging, design quality, verification practices, root-cause analysis, and system-level thinking.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.
• 8–12+ years of experience in FPGA design, IP development, or verification.
• Strong hands-on expertise in RTL design with Verilog, SystemVerilog, or VHDL, plus simulation and verification.
• Deep experience with hirify.global Quartus Prime or equivalent FPGA toolchains.
• Proven ability to debug complex system-level issues and lead technical initiatives.
• Hands-on technical depth with a leadership mindset, strong ownership and accountability, ability to simplify complex technical problems, influence without authority, and structured problem-solving.

Nice to have

• Experience with high-speed interfaces such as DDR, PCIe, or Ethernet.
• Experience with timing closure and physical implementation challenges.
• Strong understanding of FPGA architecture, resource mapping, fitter behavior, and constraints.
• Experience driving cross-team technical alignment and process or tooling improvements.

Culture & Benefits

• Hands-on technical leadership with responsibility for engineering quality and productivity.
• Regular Shift 1 schedule in Malaysia.
• Opportunity to mentor engineers and shape verification, debugging, and design practices.