Package Layout Engineer (AI)

Location: Onsite in Mountain View, California, United States.

Salary: $165,000–$225,000 per year; final compensation depends on experience, technical expertise, and role level.

Company

hirify.global is hiring for an innovative AI hardware startup developing next-generation AI accelerator systems.

What you will do

• Own end-to-end package substrate and interposer layouts, including stackup definition, bump and ball mapping, redistribution layer routing, high-density escape routing, and final design release.
• Design and optimize multi-die 2.5D and 3D packages supporting HBM interfaces and high-performance accelerator silicon.
• Develop package power and ground distribution networks for high-current accelerator requirements.
• Drive die-to-package-to-board co-design with silicon physical design, signal and power integrity, PCB layout, and packaging teams.
• Perform DRC, LVS, netlist verification, and manufacturing signoff while resolving routing, signal integrity, power integrity, and manufacturability challenges.
• Collaborate with OSAT partners and substrate suppliers and develop AI-assisted tools for layout, routing optimization, and signoff.

Requirements

• 8+ years of professional semiconductor package layout experience, ideally involving high-performance computing, AI accelerators, GPUs, or other advanced semiconductor systems.
• Strong expertise in advanced 2.5D/3D packaging and multi-die integration, including CoWoS, EMIB, InFO, fan-out, or equivalent interposer technologies.
• Hands-on experience with package substrate and interposer layout, high-density escape routing, and RDL design.
• Deep understanding of package stackup architecture, bump and ball mapping, via structures, and high-current power and ground plane design.
• Proficiency with Cadence Allegro Package Designer, Cadence SiP Layout, Siemens Xpedition Package Designer, or equivalent industry-standard package layout tools.
• Experience with package DRC/LVS verification, design rule management, and manufacturing signoff.
• Ability to collaborate with silicon architecture, physical design, SI/PI, thermo-mechanical engineering, and OSAT partners on complex package designs.

Nice to have

• Experience designing advanced packages for AI accelerators, GPUs, or high-performance processors.
• Familiarity with HBM integration, chiplet architectures, and heterogeneous multi-die systems.
• Experience with die-to-package-to-board co-design and package-level signal and power integrity optimization.
• Background working directly with semiconductor substrate suppliers and OSAT partners.
• Experience developing automation scripts or AI-assisted workflows for package layout, routing, and verification.

Culture & Benefits

• Onsite work in Mountain View, California.
• Medical, dental, and vision insurance.
• 401(k) plan.
• Employment-based visa sponsorship or transfer may be available for qualified candidates, including eligible H-1B, O-1, TN, E-3, F-1 OPT, and STEM OPT candidates.
• Reasonable accommodations are provided throughout the hiring process.