Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Крутая вакансия
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Чётко очерченная руководящая роль в быстрорастущей сфере AI-инфраструктуры с ответственностью за разработку сложных чипов; важно учитывать, что работа полностью офисная.
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Только офисAI-инфраструктураПонятная зона ответственностиВысокий порог опыта
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Physical Design Team Lead (AI Infrastructure/ASIC): Leading physical design teams through block-level and top-level implementation of complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout with an accent on timing closure, power integrity, signal integrity, and physical verification. Focus on setting technical direction, managing multi-project execution, solving cross-domain implementation challenges, and mentoring engineers in a fully in-person environment.
Location: Tel Aviv-Yafo, Tel Aviv District, Israel; other location: Haifa. The role is fully in-person.
Company
hirify.global builds semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies including CXL, Ethernet, NVLink, PCIe, and UALink.
What you will do
Lead and mentor physical design engineers, set priorities, assign work, and ensure high-quality, on-time delivery.
Drive physical design projects end to end, including planning, scheduling, risk management, and status reporting.
Define and improve physical design methodologies, flows, and best practices.
Own block-level and top-level implementation, including floorplanning, placement, clock tree synthesis, routing, and optimization.
Drive timing closure, power integrity, signal integrity, physical verification, and sign-off activities for advanced process nodes.
Partner with RTL, DFT, analog, architecture, foundry, EDA vendor, and IP provider teams through tapeout and silicon bring-up.
Requirements
10+ years of hands-on physical design experience with complex SoCs or ASICs.
Experience leading projects and technical teams through at least one full-chip tapeout.
Deep expertise with industry-standard physical design and sign-off tools, including Cadence Innovus, Synopsys Fusion Compiler or ICC2, PrimeTime, and Calibre.
Strong knowledge of timing closure, power and clock distribution, and physical verification in advanced process nodes.
Excellent communication skills and ability to work in a fully in-person, collaborative environment.
Nice to have
Experience with high-speed interface designs such as PCIe, Ethernet, or SerDes-based products.
Proficiency in Tcl, Python, or Perl for flow automation.
Experience with hierarchical design, low-power methodologies, and ECO-driven closure.
Demonstrated ability to mentor engineers and drive continuous improvement in team processes.
Culture & Benefits
Fully in-person, collaborative work environment.
Inclusive workplace welcoming people with diverse backgrounds and experiences.
Opportunity to contribute to hiring, onboarding, and professional development.
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