Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Роль четко описана и предполагает серьезную техническую ответственность за тестирование передовых чипов; узкая специализация ATE и работа в офисе в Сингапуре ограничивают круг тех, кому подойдет эта возможность.
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Узкая специализацияСовременные технологииПолный цикл задачКрупный производитель чипов
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Test Development Engineer (ATE): Developing and validating production-ready ATE test programs for NPI silicon programs with an accent on first-silicon bring-up, high-speed test hardware integration, and DFT-driven test coverage. Focus on debugging power delivery, signal integrity, firmware-hardware interaction, PVT characterization, and optimizing test time before volume manufacturing.
Location: Singapore-Yishun
Company
hirify.global is hiring for a semiconductor test development role focused on NPI silicon programs.
What you will do
Lead test strategy and architecture from pre-silicon through mass production, covering wafer sort, final test, and system-level test.
Drive first-silicon bring-up and debug issues involving power delivery, signal integrity, and firmware-hardware interaction.
Develop, implement, and validate ATE test programs on Advantest V93000/ExaScale platforms using C++, Python, and Java for test automation, characterization, and data analysis.
Collaborate with PCB and probe card designers on high-speed test hardware for PCIe Gen6, HBM4, Maxphy, and 400G+ SerDes.
Partner with design and DFT teams on Scan, MBIST, Boundary Scan, and other IP integration to improve testability, coverage, and test time.
Lead PVT characterization, product guard-band definition, test-time optimization, and cross-functional debug with IP owners, DFT engineers, and assembly/test partners.
Requirements
Proven experience developing ATE test programs on Advantest SmartScale (PS1600) or ExaScale (PS5000) platforms.
Advanced programming skills in C++, Python, and Perl, with the ability to write robust and maintainable test code.
Deep understanding of silicon physics, ESD, latch-up, and testing challenges at advanced 1.4nm, 2nm, and 3nm nodes.
Strong knowledge of high-speed electronics, transmission line theory, power delivery, and test hardware design, including loadboards, sockets, and thermal control.
Demonstrated success navigating NPI milestones from tape-out through qualification and high-volume transfer.
Culture & Benefits
Full-time employment in Singapore-Yishun.
Equal opportunity employment under applicable local, state, and federal laws.
Applicants located outside the USA should provide a home address for future correspondence.
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