Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
Очень мало
72к-99к CAD/год
110к CAD130к CADмедиана190к CAD
По похожим ролям (42) ~ 130к CAD/год
На СНГ рынке: $1.8к/мес ($1.4к - $3к)
78
Хорошая вакансия
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Чётко очерченная инженерная роль в крупном производителе чипов даёт возможность разрабатывать Ethernet IP и работать с разными инженерными командами; стоит учесть обязательный офисный формат.
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Ниже рынкаЧёткие задачиКрупный производитель чиповСовременный EthernetРабота в офисе
Оценка от Hirify AI
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Logic Design Engineer (Ethernet): Architecting and implementing Ethernet and networking IP for next-generation SoCs in automotive, industrial, and edge computing markets with an accent on scalable micro-architecture, Verilog RTL, synthesis, and timing closure. Focus on implementing complex hardware algorithms, completing front-end quality checks, and coordinating IP integration with verification and SoC implementation teams.
Location: Kanata/Ottawa, Canada; onsite role
Base salary: $72,000–$99,000 CAD per year
Company
hirify.global develops semiconductor products and advanced microcontroller, microprocessor, networking, automotive, IoT, and radio-frequency technologies.
What you will do
Architect, design, and implement Ethernet and networking IP for next-generation SoCs used in automotive, industrial, and edge computing markets.
Develop micro-architecture and Verilog RTL, and perform logic synthesis and timing closure.
Analyze performance, area, and complexity trade-offs while creating scalable and parameterized IP.
Execute IP quality checks, including Lint, CDC, Synthesis, STA, and LEC, through front-end to back-end handoff.
Collaborate with verification, architecture, software, marketing, SoC integration, implementation, and application engineering teams.
Provide technical support, participate in code reviews and project planning, maintain documentation, and drive design-methodology improvements.
Requirements
Bachelor’s degree in Computer Science, Engineering, or related education.
Knowledge of Verilog RTL design, logic synthesis, coverage analysis, and timing closure.
Understanding of IP development methodology and proficiency with front-end design tools.
Ability to understand hardware and software implementation trade-offs and solve system-wide problems.
Ability to work effectively in a team environment.
Strong interpersonal, communication, and documentation skills.
Nice to have
Experience designing complex digital IP using RTL.
Knowledge of networking technologies, including TCP/IP protocols.
Experience with data products such as routers, bridges, and switches.
Security or cryptography experience.
Strong architecture and design skills.
Algorithm development experience.
Culture & Benefits
Work within an experienced R&D team and a central advanced chip engineering organization.
Contribute to IP used in automotive, IoT, networking, and radio-frequency products.
Health, dental, vision, wellness, savings programs, and RRSP.
Competitive benefits, incentive compensation, and equity for certain roles.
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