Design Engineer Intern (SoC/RTL)

Location: Yokneam, Israel

Company

hirify.global develops semiconductor solutions for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Work with the SoC-level team on switching SoC projects.
• Design and implement new features across RTL design.
• Integrate IP blocks into the SoC based on functionality, interfaces, and requirements.
• Develop automation flows using Python, Perl, and TCL to reduce manual effort and improve design and verification efficiency.
• Collaborate with verification, physical design, firmware, and software teams on system-level integration.
• Investigate simulation and integration failures, identify root causes, and drive resolutions; participate in IP block and multidisciplinary system design and verification.

Requirements

• Currently pursuing a bachelor's or master's degree in computer science, electrical engineering, or a related field, with at least two years before graduation.
• Must be in the second year of study or above.
• Ability to maintain an overall top-down system view.
• Good interpersonal skills and ability to work in a team.
• Excellent problem-solving ability.
• Well-organized documentation and research process.
• Clear and concise communication and presentation skills.
• Self-learning skills and strong motivation to achieve project goals.
• Must be eligible to access export-controlled information under applicable U.S. export control laws; applicants may be subject to an export license review process before employment.

Culture & Benefits

• Competitive compensation and benefits.
• Collaborative, transparent, and inclusive work environment.
• Tools and resources to support meaningful work, learning, and professional development.
• Interviews prohibit the use of AI tools, transcription applications, automated answer generators, and automated note-taking bots unless specifically permitted by the interviewer.