CPU IP Design & Verification Engineer (RISC-V)

Location: Austin, Texas, or Santa Clara, California, United States

Salary: $86,000–$170,000 per year

Company

hirify.global manufactures essential semiconductors and develops semiconductor solutions for AI and other high-growth markets.

What you will do

• Design and develop RISC-V CPU microarchitecture and SystemVerilog RTL.
• Contribute to instruction fetch and decode, execution, load/store, caches, memory interfaces, control and status registers, exceptions, and interrupts.
• Develop verification tests, assertions, checkers, and functional coverage for CPU features.
• Run simulations and regressions; debug failures using logs, architectural traces, and waveforms.
• Support functional and coverage closure, CPU power, performance, and area analysis and optimization.
• Develop Python, C/C++, or scripting-based automation and collaborate across architecture, design, verification, performance, and implementation teams.

Requirements

• Graduating with a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field from an accredited degree program.
• Overall GPA of at least 3.0 and good academic standing.
• English fluency in written and verbal communication.
• Strong foundation in digital logic design and computer architecture.
• Coursework, research, internship, or project experience with Verilog or SystemVerilog.
• Understanding of CPU fundamentals, including pipelines, instruction execution, loads/stores, caches, and memory hierarchy.
• Programming or scripting experience with Python, C/C++, or similar languages.
• Strong analytical, problem-solving, and debugging skills.

Nice to have

• Related internship or co-op experience.
• Leadership experience in workplace, school projects, or competitions.
• Project management, innovation, execution, and ambiguity-navigation skills.
• Strong written and verbal communication, planning, and organizational skills.
• Knowledge of the RISC-V Instruction Set Architecture.
• Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification.
• CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience.
• Familiarity with caches, memory subsystems, privilege modes, exceptions, interrupts, or virtual memory.
• Experience with simulation, waveform debug, Git, and Linux.
• Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis.
• Assembly-language programming experience.
• Interest in AI-assisted engineering tools for RTL design, verification, automation, and debug productivity.

Culture & Benefits

• Full-time employment for new college graduates in a fast-paced work environment.
• Accelerated training, mentorship, networking, and leadership opportunities.
• Cross-functional collaboration and talent mobility.
• Safe and responsible work practices supporting Environmental, Health, Safety & Security programs.