Sort Interface Pathfinding and Development Engineer (Advanced Packaging)
Контакты
133 800 - 255 200$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
pcbsemiconductordesign of experimentsadvanced packagingprobe cardwafer sortautomated test equipmentdie sort
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
Пожаловаться
Зарплата и рынок
$134к-255к/год
$180к$200кмедиана$220к
По похожим ролям (50) ~ $200к/год
87
Хорошая вакансия
развернуть
Чётко очерченная инженерная роль в крупной полупроводниковой компании связана с передовыми технологиями упаковки чипов; главный компромисс - обязательная работа на площадке в Хиллсборо.
Кликните для подробной информации
Понятные задачиПередовая упаковкаРабота на площадке
Оценка от Hirify AI
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Подключить Plus
Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Sort Interface Pathfinding and Development Engineer (Advanced Packaging): Developing silicon interface probing and test solutions for wafer and die sort across advanced packaging platforms including EMIB, EMIB-T, Foveros, and Foveros Direct with an accent on electro-mechanical pathfinding, test hardware development, and probing process qualification. Focus on designing experiments, translating chiplet and package requirements into scalable interface specifications, and coordinating customers, suppliers, and manufacturing readiness for new product introductions.
Location: On-site in Hillsboro, Oregon, United States
Annual salary: $133,800–$255,200 USD
Company
hirify.global develops semiconductor, computing, connectivity, and artificial hirify.globalligence technologies. The Advanced Packaging, Test and Manufacturing organization delivers packaging and test technologies for Client, Data Center, AI, Networking, and External Foundry markets.
What you will do
Develop silicon interface probing and test solutions for wafer and die sort across advanced process nodes and heterogeneous packaging platforms including EMIB, EMIB-T, Foveros, and Foveros Direct.
Formulate and execute Design of Experiments to optimize and qualify probing technologies, contact architectures, probing margins, yield, and process health.
Translate chiplet and package requirements from Foundry and OSAT customers into scalable sort interface specifications.
Create sort design rules and Interface Design Kits for external fabless customers and design partners.
Architect test interface hardware with customer design and DFT teams and resolve technical gaps.
Coordinate global test solution vendors and PCB suppliers, drive supplier accountability, and support manufacturing readiness for New Product Introductions.
Requirements
Bachelor’s degree in electrical engineering, mechanical engineering, materials science, or a related STEM field with 6+ years of industry experience, or a master’s degree with 4+ years of industry experience, or a Ph.D. with 2+ years of relevant post-graduate or industry experience.
Experience with wafer or die sort technology, prober-tester cell integration, and qualification of advanced probe card technologies.
Experience structuring and executing Design of Experiments to evaluate probing margins, yield, and process health.
Direct experience in ATE test hardware or methodology, Sort/Class product development, or PCB, space transformer, or substrate design rules and stackup architectures.
Collaborative communication skills for working with cross-functional teams, customers, and global suppliers.
Ability to translate complex technical concepts into clear, actionable specifications and make data-driven decisions in an evolving environment.
Nice to have
6+ years of experience in advanced probing process characterization.
Experience managing technical relationships with external probe card or substrate suppliers or supporting external Foundry and OSAT customers with test hardware applications.
Knowledge of OSAT and Foundry test operations, multi-client test cell standards, customer design collateral, PDK enablement, or turnkey test delivery models.
Experience qualifying probe technologies for fine-pitch micro-bumps, 2.5D/3D architectures, EMIB, EMIB-T, silicon bridges, or wafer-level chip-scale probing.
Hands-on experience with Advantest V93k or Teradyne Ultra-FLEX ATE platforms.
Culture & Benefits
Full-time, experienced-hire position with on-site work required.
Competitive annual compensation with stock bonuses.
Health, retirement, and vacation benefits.
Work involves collaboration with customers, suppliers, and global cross-functional teams.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →