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5 дней назад

R&D Engineer

167 500 - 268 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

R&D Engineer (Semiconductor Advanced Packaging): Owns advanced packaging and system-in-package assembly technology roadmaps, translating system-level performance requirements into modules while collaborating with internal IC teams and external foundry/OSAT partners. Focus on solving leading-edge AI/HPC module packaging challenges with hands-on evaluation, qualification planning, reliability failure mechanism analysis, and risk mitigation from concept through transfer to high-volume manufacturing.

Company

hirify.global develops semiconductor and infrastructure technologies.

What you will do

  • Lead multi-chip semiconductor assembly and system pathfinding for leading-edge AI and high-performance computing modules.
  • Drive development of new assembly technology from early R&D through product introduction, owning key parts of the advanced packaging and assembly roadmap.
  • Define technology requirements, evaluation and qualification plans, and provide hands-on support during transitions from process R&D to product development.
  • Lead advanced packaging technology problem solving, including design and product enablement.
  • Manage projects independently from concept through transfer to high-volume manufacturing, coordinating internal and external collaborators.
  • Perform risk assessment and coordinate cross-functional risk mitigation across multiple parallel technology projects.

Requirements

  • Location: San Jose, CA (USA)
  • MSEE in Electrical Engineering or related field required.
  • 15+ years of experience in semiconductor process technology and advanced packaging/manufacturing in R&D and integration roles, or PhD with 12+ years in the same domain.
  • Broad knowledge of advanced packaging/assembly and silicon process technologies, including thermal solutions, power delivery, and electrical/optical communication.
  • Experience with serial and parallel interface design for chip-to-chip and external module communication.
  • Experience with parametric/yield data analysis and root-cause finding tools for yield failure mechanisms (EFA, PFA), plus thermal and stress simulation tools.

Culture & Benefits

  • Annual base salary range: $167,500–$268,000.
  • Discretionary annual bonus and potential new-hire equity grant and annual equity awards.
  • Medical, dental, and vision plans; 401(k) participation with company matching; ESPP; EAP.
  • Paid holidays, paid sick leave, and vacation time; paid family leave and other leaves per applicable laws.
  • Equal opportunity employer.

Hiring process

  • Create a candidate login account (if first time) and sign in before applying.
  • Application review followed by interview steps as determined during the hiring process.

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