Principal NPI Product Engineer (Semiconductor)

Location: Stockholm, Sweden; hybrid, 4 days a week in the office.

Salary: 7000.000 SEK – 1,000.000 SEK.

Company

hirify.global develops high-speed CMOS and BiCMOS ICs for optical infrastructure supporting AI data centers, cloud platforms, and global communications.

What you will do

• Own NPI programs from product concept and first silicon through final release and transfer to full-volume manufacturing.
• Lead milestone reviews, release deliverables, and OSAT manufacturing documentation.
• Define DfT and DfM requirements and lead development and optimization of ATE test programs.
• Set datasheet specifications and production test limits using characterization and statistical analysis.
• Plan wafer-level and bench testing across PVT conditions, lead ATE-to-bench correlation, process capability studies, yield modeling, DOE, and reliability qualification.
• Monitor yield and quality, lead failure analysis and root-cause investigations, drive CAPA, and deliver lifecycle cost reductions with foundry, packaging, and OSAT partners.

Requirements

• Bachelor's degree in Electrical Engineering or a related field; a Master's degree is strongly preferred.
• 8+ years of experience in semiconductor product engineering, test engineering, or design engineering.
• Proven ownership of silicon bring-up, characterization, and production transfer programs.
• Hands-on experience with ATE test development, ATE-to-bench correlation, and production test limit setting.
• Strong foundation in DfT and DfM principles.
• Proficiency with statistical analysis tools such as JMP or Excel, plus scripting or automation in Python, TCL, or equivalent.
• Fluent professional English, written and spoken.
• Excellent analytical, problem-solving, and cross-functional communication skills.

Nice to have

• Background in analog/mixed-signal or optical IC characterization, including TIA, CDR, LimitAmp, or high-speed SerDes.
• Familiarity with high-speed ATE platforms such as Advantest or Teradyne.
• Experience with JEDEC reliability qualification methodologies, including HTOL, HAST, ESD, and latch-up.
• Exposure to ATPG, MBIST, or boundary scan DFT flows.
• Experience engaging directly with foundry and OSAT partners.

Culture & Benefits

• Work on CMOS and BiCMOS ICs supporting 400G, 800G, and 1.6T optical networking and AI infrastructure.
• Collaborate with colleagues across Burlington, Bristol, Aguascalientes, San Diego, and the Asia Hub from Stockholm.
• Work directly with design, reliability, and fab teams in a technically rigorous, cross-functional environment.
• Receive competitive compensation, benefits, and professional development opportunities.
• Shape technical strategy, mentor others, and develop toward broader architecture or engineering leadership.