Principal Analog/Mixed Signal CAD Engineer - EMIR

Location: Santa Clara, CA or Irvine, CA; onsite five days per week. Remote and hybrid work are not available.

Salary: USD 150,680–225,700 per annum.

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, carrier, networking, and connectivity infrastructure.

What you will do

• Develop and support electromigration and IR-drop analysis flows, including flow setup, DSPF validation, current-density and voltage-drop analysis, debugging, and post-layout verification.
• Architect and support automated analog/mixed-signal design flows used across design teams.
• Build and maintain custom tools, PCells, Pycells, GUI utilities, and automation tools in Cadence Virtuoso, Synopsys OptoCompiler, and Siemens Calibre environments.
• Install and validate foundry PDKs and maintain physical verification, parasitic extraction, and EMIR flows.
• Partner with analog designers, EDA vendors, foundry partners, and modeling specialists to resolve complex design-flow challenges.
• Help shape company-wide CAD infrastructure and best practices for analog, mixed-signal, and silicon photonics development.

Requirements

• Hands-on experience with Cadence Voltus-XFi.
• BSEE with 10–15 years of professional experience, or MS/PhD in Electrical Engineering with 5–10 years of industry experience.
• Experience building and maintaining analog/mixed-signal design flows for advanced FinFET, BiCMOS, SiGe, and SiPho technologies.
• Hands-on experience with Cadence Virtuoso Studio, Synopsys OptoCompiler, and Siemens Calibre.
• Understanding of schematic capture, simulation, parasitic extraction, post-layout verification, and EMIR.
• Programming or scripting experience in Python, TCL, Shell, and SKILL.
• Experience developing custom CAD automation or verification frameworks.
• Familiarity with silicon photonics design flows.
• Excellent communication and cross-functional collaboration skills.

Nice to have

• Experience with electromagnetic simulation and extraction.

Culture & Benefits

• Work with advanced FinFET, BiCMOS, SiGe, and SiPho semiconductor technologies.
• Influence CAD methodologies and infrastructure used across multiple product lines and engineering teams worldwide.
• Collaborate with designers, modeling experts, foundry partners, and EDA vendors.
• Eligibility for bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
• Benefits include an employee stock purchase plan, family support programs, mental health resources, and recognition awards.

Hiring process

• Interviews evaluate individual experience, thought process, and communication skills in real time.
• AI tools, transcription apps, automated answer generators, and automated note-taking bots are not permitted during interviews.
• The role may require export-license review for access to U.S. export-controlled technology or software.