Silicon Validation Intern (Semiconductor)

Location: Santa Clara, CA

Expected base pay: $28–$56 per hour

Company

hirify.global develops semiconductor solutions for enterprise, cloud and AI, and carrier data infrastructure.

What you will do

• Support post-silicon validation of high-speed rack-scale switch silicon under the guidance of senior engineers.
• Develop, document, and execute test plans and test cases for switch chip validation.
• Support lab-based silicon bring-up and run unit tests on hardware and firmware functionality, including emulation and verification environments.
• Collect and analyze high-speed signal and link data, including eye diagrams, jitter, and BER, using lab equipment.
• Debug silicon and hardware issues, troubleshoot switch performance and efficiency, and use diagnostics, oscilloscopes, and protocol analyzers to isolate root causes.
• Write and maintain scripts to automate test execution, data collection, and result reporting; document findings and present debug progress to the team.

Requirements

• Currently pursuing a bachelor’s degree in electrical engineering, computer engineering, computer science, or a related field, with expected graduation between Fall 2027 and Summer 2028.
• Foundational understanding of digital logic, computer architecture, and high-speed I/O concepts such as SerDes and PCIe or Ethernet protocols.
• Basic hands-on lab experience through coursework, research, or projects, including hardware bring-up, testing, and debugging.
• Familiarity with oscilloscopes, logic analyzers, or BERTs.
• Programming or scripting experience in Python, Perl, or a similar language.
• Strong analytical, problem-solving, and communication skills, with a willingness to learn.
• Applicants must be eligible to access export-controlled information under applicable U.S. laws; applicants who are not U.S. citizens, lawful permanent residents, or protected individuals may be subject to an export license review.

Nice to have

• Coursework or project experience with PCIe, Ethernet, or other high-speed interfaces.
• Exposure to the physical and protocol layers of high-speed interfaces, such as PHY, PCS, and MAC.
• Experience with emulation, simulation, or verification environments.
• Ability to read board schematics and layouts.
• Familiarity with signal integrity concepts such as eye diagrams, jitter, and BER.

Culture & Benefits

• Work alongside experienced engineers on AI and cloud data center networking products.
• Medical, dental, and vision coverage for interns.
• Perks and discounts, mental health resources, and paid holidays.
• Additional compensation may be available for intern PhD candidates.

Hiring process

• Interviews are designed to assess individual experience, thought process, and communication skills in real time.
• AI tools, transcription apps, real-time answer generators, and automated note-taking bots are not permitted during interviews.