Staff Embedded Software Engineer

Location: London, UK. On-site, full-time role. Due to U.S. export control regulations, eligibility depends on the candidate's most recent citizenship or permanent residency status; applicants whose most recent citizenship or permanent residence is in Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, or Venezuela are generally not eligible unless they later obtained citizenship or permanent residency in an unrestricted country.

Salary: Starting from £300K, plus equity. Additional compensation includes competitive salary based on experience, skills, and location, meaningful stock options, an annual Living-Local Bonus for residing within 20 minutes of the office, and employer-contributed retirement plans.

Company

hirify.global develops the DX-1 decode accelerator, a rack-scale custom silicon platform designed to improve AI infrastructure performance and efficiency through co-design of logic, data movement, packaging, optics, and interconnect.

What you will do

• Lead a major area of DX-1 platform firmware, such as boot and update, platform management, or register-level ASIC control, owning its design, interfaces, roadmap, and production delivery.
• Define explicit contracts and interfaces covering register maps, update flows, telemetry, and other dependencies between firmware, FPGA, ASIC, and systems software teams.
• Support platform bring-up and validation from pre-silicon simulation and FPGA prototypes through first silicon and production, diagnosing boot, driver, and management-plane issues.
• Define fault containment, logging, failure recovery, power sequencing, and interrupted firmware-update behaviour.
• Build reusable reference implementations, firmware tests, validation infrastructure, and device-model contributions.
• Identify high-impact technical risks, review senior engineers' designs and code, develop engineers, and participate in hiring.

Requirements

• Depth across the hardware-software boundary, including bare-metal or RTOS firmware on resource-constrained cores and embedded Linux BSP development with Yocto/OpenEmbedded, U-Boot or UEFI, drivers, and device tree.
• Strong systems fundamentals covering memory ordering and barriers, coherent and non-coherent shared memory, synchronization with and without atomics, interrupt latency, and timing and memory-bandwidth budgets.
• Experience taking firmware through silicon or board bring-up, from pre-silicon simulation or emulation and FPGA prototypes through first power-on, with the ability to explain issues and their diagnosis.
• Platform-management experience in a rack-scale context, including OpenBMC or equivalent, Redfish, PLDM over MCTP, I2C/SMBus/PMBus, SPI, UART, power sequencing, and fault isolation.
• Experience with register-level control of an ASIC or large FPGA over a management link, including use of a simulation model before silicon exists.
• Technical leadership without formal authority, demonstrated through a specification, methodology, or tool adopted and used by teams outside the candidate's own team, together with the design document behind it.
• Outstanding technical communication skills, including explaining architectural decisions and consequences to engineers, managers, and senior leadership and writing design documents that other teams can build from.

Nice to have

• Experience across more than one hardware generation or with firmware for an ASIC whose tape-out the candidate helped deliver.
• Experience with IEEE 1588 PTP, White Rabbit, SyncE, SerDes or optical link bring-up, or secure boot.

Culture & Benefits

• On-site work in London with a proximity-focused annual bonus for living within 20 minutes of the office.
• Meaningful stock options and ownership in the company.
• Employer-contributed retirement plans.
• Hands-on individual-contributor role with close collaboration across FPGA, ASIC, systems software, and embedded engineering teams.