Engineering Manager - FPGA & Hardware - Enforced Security (FPGA)

Location: Tampa, Florida, United States. The role requires a US person—United States citizen or lawful permanent resident—eligible for a security clearance.

Company

hirify.global develops cybersecurity products for protecting IT, OT, and ICS critical infrastructure, including the MetaDefender NetWall hardware-enforced security gateway.

What you will do

• Own the FPGA discipline for the NetWall product line, including RTL architecture, verification, timing closure, coding standards, IP selection, toolchains, and regression infrastructure.
• Select FPGA silicon and commercial boards based on sustained line rate, transceiver capacity, PCIe generation, optical compatibility, lead time, and licensing cost.
• Build one-way gateware datapaths with framing, link supervision, fail-closed behavior, and receiving-side reassembly.
• Implement hardware protocol termination, including TCP state machines and future TLS termination and re-origination without an acknowledgement path across the boundary.
• Own UVM, constrained-random, coverage-driven, and formal verification, including certification evidence and requirements traceability.
• Build and lead the FPGA organization, recruit senior engineers, establish the bring-up lab, and grow two independent implementation teams.

Requirements

• At least five years of FPGA development experience, including production RTL in a shipping product and experience leading or managing FPGA engineers.
• Deep SystemVerilog or VHDL experience with ownership of architecture, verification, and timing closure on large designs.
• Experience with multi-gigabit transceivers, Ethernet MAC and PCS, PCIe endpoints, DMA, and hardware protocol implementation.
• Experience with UVM, constrained-random and coverage-driven verification, formal property verification, and AMD Vivado or Altera Quartus Prime Pro.
• Technical understanding of Linux drivers, networking, security architecture, and system performance across hardware and software boundaries.
• US person status and eligibility for a security clearance are required. Professional fluency in English is required.

Nice to have

• Experience with cross-domain solutions, data diodes, guards, or other high-assurance security hardware.
• Common Criteria, FIPS 140-3, or NCDSMO Raise the Bar experience.
• Active US security clearance and formal verification of security properties.
• Experience with 100 Gbps networking, TCP offload, TLS acceleration, or both AMD and Altera toolchains.
• Experience in critical infrastructure, OT, industrial, avionics, rail, or nuclear environments.

Culture & Benefits

• Work on an installed security gateway base across energy, manufacturing, defense, government, transportation, and healthcare.
• Extend an existing Common Criteria EAL4+ certification and certified optical isolation hardware.
• Join an R&D organization of approximately 50 engineers and build on the MetaDefender platform.
• Lead a funded multi-year program targeting 100 Gbps and NCDSMO Raise the Bar requirements.
• Receive budget and hiring authority to establish the FPGA team outside the standard requisition process.