Intern (SRAM Development and Methodologies)

Location: Valbonne (Sophia-Antipolis), France; full-time, on-site. Duration: 6 months, starting in early Q1 2027.

Company

hirify.global develops electronic design software, hardware, and IP for chips, boards, and systems used in consumer, computing, communications, automotive, aerospace, industrial, and health applications.

What you will do

• Select and work on one of three topics: advanced SRAM design and self-timing optimization; statistical yield optimization for next-generation SRAM memories; or power characterization methodology for memory compilers.
• Analyze process variations, SRAM yield, robustness, timing paths, and performance, power, and area trade-offs.
• Study and benchmark bitcell-based, hybrid, and other timing-tracking architectures and yield-allocation strategies.
• Develop simulation, evaluation, variation-aware design, optimization, characterization, and interpolation methodologies.
• Review power stimuli, critical signals, initialization sequences, simulation settings, memory power modes, and compiler architectures.
• Validate architectural improvements, Liberty power trends, and methodologies across different memory sizes, configurations, features, and compiler types, including single-port, dual-port, and ROM.

Requirements

• Final-year engineering or Master's student, or pursuing an equivalent qualification, in microelectronics, electronics, computer engineering, computer science, applied physics, data science, or a related discipline.
• Foundational knowledge or interest in microelectronics, CMOS circuit design, and SRAM architecture.
• Knowledge or interest in VLSI design, advanced technologies, circuit simulation, variability analysis, statistical analysis, power analysis, EDA methodologies, and memory compiler architectures.
• Data analysis and scripting skills, preferably Python, Tcl, or Shell.
• Curiosity, enthusiasm, willingness to learn, problem-solving ability, logical reasoning, analytical skills, and a methodical mindset.
• Good presentation skills.

Culture & Benefits

• Six-month, hands-on internship in industrial memory IP development.
• Exposure to advanced-node design, high-sigma statistical analysis, yield optimization, transistor-level power analysis, electrical characterization flows, and power-modeling methodologies.
• Opportunity to contribute to memory methodologies for next-generation embedded memory, AI, and high-performance computing products.