E-core CPU Full Chip Physical Design Engineer

Location: Penang, Malaysia; hybrid work model with time split between the assigned hirify.global site and off-site work.

Company

hirify.global develops CPU and semiconductor technologies, including future-generation processor designs.

What you will do

• Construct, integrate, and verify full-chip assemblies of CPU partitions.
• Perform floorplanning, pin and feedthrough planning, repeater insertion, power grid generation, and partition assembly.
• Drive physical design and timing closure, including FEV, LVS, DRC, IR drop, and electromigration analysis.
• Improve full-chip methodology efficiency, quality, floorplan utilization, quality of results, and runtime.
• Coordinate collateral handoffs with Clocking, Power Delivery, and Partition Synthesis/APR teams.
• Collaborate across functional teams while delivering multiple projects under aggressive schedules.

Requirements

• BS or MS degree in Electrical Engineering or Computer Engineering.
• At least 7 years of experience in CPU physical design and timing verification.
• Experience with synthesis/APR flows for multivoltage, high-frequency designs, including custom polygon editing.
• Experience with Tcl scripting, noise, crosstalk, and OCV analysis.
• Experience with floorplanning, physical design, timing closure, formal equivalence, DRC/LVS, IR, and electromigration checks.
• Willingness to work in the hybrid model associated with the hirify.global site in Penang, Malaysia.

Nice to have

• Experience with Fusion Compiler, RedHawk, ICV, Conformal, Calibre, PrimeTime, or StarRCXT.

Culture & Benefits

• Full-time experienced-hire position.
• Hybrid work model combining on-site and off-site work.
• Collaborative work across CPU backend design functions.
• Commitment to equal employment opportunity and ethical hiring practices.
• No recruitment, medical examination, or other hiring fees are charged to candidates.