Photonic IC Layout & Design Flow Engineer (AI)

Location: United States; conditions mention Berkeley, California, the San Francisco Bay Area, Boston, Massachusetts, and Texas

Salary: $160,000–$250,000 per year; additional listed salary ranges include $150,000–$220,000, $200,000–$300,000, $260,000–$300,000, and up to $250,000 base

Company

hirify.global is hiring for a photonic computing company developing an integrated optical-electronic platform for AI workloads.

What you will do

• Own chip-level photonic IC layout, component integration, PDK checks, DRC/LVS, signoff, and tape-out readiness.
• Establish and improve the Cadence-based photonics workflow for the GlobalFoundries 45 nm process.
• Build repeatable PDK, layout, and verification workflows for complete chip delivery.
• Integrate the photonic design flow with electronic IC development and resolve PIC, EIC, and packaging interface requirements.
• Work with measurement and characterization engineers to connect silicon results with design improvements.
• Provide technical direction to photonic engineers while remaining hands-on with implementation and verification.

Requirements

• At least one complete industry PIC tape-out with direct responsibility for chip-level layout, verification, and signoff.
• Strong practical experience with Cadence Photonics, Virtuoso, or a closely related commercial PIC flow.
• Experience building or improving design flows rather than only using an established workflow.
• Strong understanding of silicon-photonics device physics, with meaningful device or circuit design and simulation experience.
• Practical collaboration experience with electronic IC, packaging, measurement, and characterization engineers.
• Ability to coordinate specialist designers and remain accountable for complete chip delivery.

Culture & Benefits

• Direct access to founders and close collaboration across photonics, electronics, packaging, and lab validation.
• Opportunity to shape engineering workflows and decisions that move research silicon toward a commercial system.
• The first six months focus on completing the Cadence Photonics workflow and integrating it with the EIC design flow.