Senior NoC Research Engineer (Network-on-Chip)

Location: Remote from Germany; role associated with Dresden, Germany. Up to two weeks of work abroad annually.

Company

hirify.global develops brain-inspired computing hardware and software based on SpiNNaker2 technology, providing remote access to sparse computing resources for AI and HPC.

What you will do

• Explore NoC topologies, router and switch designs, arbitration, flow control, QoS, congestion control, and adaptive routing.
• Build and maintain architectural models and simulations using SST, gem5, and custom cycle-level or analytical models.
• Develop traffic generators representing collective communication, tensor parallelism, and memory traffic in machine-learning workloads.
• Analyse power, performance, and area trade-offs and provide quantitative design recommendations.
• Translate AXI, CHI, and APB specifications into design requirements while evaluating interconnect IP and chip-to-chip interfaces.
• Present research findings to architecture and leadership teams and contribute to publications and patents.

Requirements

• PhD, or a Master’s degree with equivalent research experience, in electrical engineering, computer engineering, computer science, or a related field.
• Senior-level experience in NoC or interconnect architecture in industry or applied research.
• Strong knowledge of NoC topologies, routers, switches, arbitration, flow control, QoS, and congestion control.
• Understanding of machine-learning workloads, accelerator architectures, RDMA concepts, InfiniBand, RoCE, and on-chip protocols such as AXI, CHI, or AHB.
• Hands-on experience with architectural modelling and simulation, plus strong Python and C++ skills.
• Clear written and verbal communication in English is required.

Nice to have

• Experience with PCIe, Ethernet, UCIe, HBM, CXL, or massively parallel architectures.
• Publications or patents in on-chip networks, interconnect architecture, data movement, ML, or HPC.

Culture & Benefits

• Work on sparse-computing technology with direct influence on the SpiNNext architecture.
• Collaborate with engineers from academia and industry.
• 30 days of annual vacation.
• Up to two weeks of work abroad per year.
• Equity participation in a growing deep-tech company.

Hiring process

• Submit a CV, a brief cover letter describing an analysed interconnect or data-movement problem, and optional links to publications, patents, or public code.
• Include salary expectations, earliest start date, current location, and whether visa sponsorship or relocation support to Germany is needed.