SRAM/ROM Circuit Design Engineer

Location: Austin, Texas; office-based with at least 3 days per week in the office

Company

hirify.global develops SRAM and ROM memory compiler solutions within its Design Enablement/Foundation IP organization for SoC design teams across multiple business lines.

What you will do

• Design CMOS SRAM and ROM memory circuits and supporting periphery to meet performance, power, and area requirements.
• Implement circuit functionality for functional safety and scan operations.
• Generate, execute, and evaluate simulation characterization measurements and test benches against performance targets.
• Collaborate with layout teams on compiler leaf-cell implementation to improve area and performance.
• Work with CAD teams to integrate designs into characterization, verification, and regression flows.
• Align with modeling and verification teams on behavioral, ATPG, and emulation frontend models, while collaborating with global memory teams and applying GenAI tools to design methodologies.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related discipline; a Master’s degree is preferred.
• 8+ years of industry experience in SRAM memory circuit design, or 6+ years with a Master’s degree.
• Experience designing with advanced CMOS foundry technologies at 5nm and beyond.
• Strong familiarity with Cadence Virtuoso and other standard EDA tools.
• Ability to work from the NXP offices in Austin, Texas at least 3 days per week.
• Strong analytical and problem-solving skills, with scripting experience in Perl, Tcl, or Python.

Nice to have

• Familiarity with automotive design rules and memory design requirements.
• Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.

Culture & Benefits

• Work within a global memory engineering organization.
• Collaborate across design, layout, CAD, modeling, and verification teams.
• Use internally supported LLM/GenAI tools and EDA vendor GenAI solutions to improve design methodologies.