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9 дней назад

Senior Methodologist for AIML Enhanced Design/Verification (AI)

174 000 - 352 500$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Senior Methodologist for AIML Enhanced Design/Verification (AI): Developing AI-enhanced agents, infrastructure, and verification methodologies for complex digital designs from RTL through tapeout, with an accent on SystemVerilog, UVM, RTL generation, and verification closure. Focus on architecting agentic design and verification solutions, automating RTL generation from specifications, analyzing failures, and evaluating industry tools.

Location: Onsite, primarily from an HPE office; the stated salary range applies to the United States, including California

Salary: USD 174,000–352,500 annual base salary in California, United States. Variable incentives may also be offered.

Company

hirify.global is a global edge-to-cloud technology company developing solutions for connecting, protecting, analyzing, and acting on data and applications.

What you will do

  • Develop and execute verification strategies for complex digital designs using classical, generative-AI, and agentic methodologies.
  • Architect, build, and maintain AI-enhanced agents, skills, APIs, models, and infrastructure for design and verification.
  • Create or enhance UVM-based testbench environments, verification plans, coverage goals, and closure criteria.
  • Perform root-cause analysis of failures and collaborate with design and system engineering teams from RTL through tapeout.
  • Automate RTL generation from specifications and evaluate industry design and verification tools.

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or an equivalent field.
  • 3–5 years of hands-on experience with AIML methods, concepts, workflows, agents, skills, APIs, and models for design or verification problems.
  • 5–7 years of production experience developing RTL design and verification infrastructure.
  • Strong SystemVerilog experience and solid understanding of RTL, digital design fundamentals, timing, and synthesis constraints.
  • Experience with industry-standard simulation tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
  • Effective communication and collaboration skills in cross-functional engineering teams.

Nice to have

  • Master's or Ph.D. in Electrical Engineering or Computer Science.
  • Experience with formal verification tools and techniques, including JasperGold or VC Formal.
  • Experience with emulation and FPGA prototyping platforms such as Palladium, Protium, or Veloce.
  • Industry conference or peer-reviewed journal publications in design and verification methodology development or AIML.

Culture & Benefits

  • Health, financial, and emotional wellbeing benefits for employees and their families.
  • Personal and professional development programs supporting career growth and specialization.
  • Inclusive workplace committed to accessibility and equal employment opportunity.
  • Work on challenging silicon and design-verification projects with a focus on innovation, quality, and continuous learning.

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