Assoc Eng Integration & Yield (Oct Rec Drive 2026)

Location: Woodlands, Singapore; onsite in a semiconductor fabrication environment

Company

hirify.global provides semiconductor design, development, and fabrication services through a global manufacturing network.

What you will do

• Analyze inline defect data from inspection and SEM review tools.
• Troubleshoot affected process tools and support shutdown decisions based on data analysis.
• Review and disposition lots inspected through YDD, ensuring out-of-control lots remain on hold during troubleshooting.
• Support process modules, yield engineering, process integration, and technology development teams with inline defect analysis.
• Check daily YDD scan maps and out-of-control points from SPC charts.
• Manage overall WIP control and create recipes for Rudolph and KLA Brightfield and Darkfield inspection tools.

Requirements

• Diploma in Electrical/Electronics Engineering or a related technical field.
• 1–3 years of relevant semiconductor fabrication experience; fresh diploma holders may also be considered.
• Willingness to work 12-hour rotating shifts is required; permanent night shift experience is an advantage.
• Good interpersonal and communication skills.
• Ability to work effectively as part of a team.

Culture & Benefits

• Work in a multicultural and inclusive manufacturing environment.
• Support environmental, health, safety, and security requirements.
• Employment is subject to applicable background checks, medical screenings, and local laws.
• No recruitment fees are charged at any stage of the hiring process.