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11 дней назад

Process Control Defectivity Engineer (Semiconductor Manufacturing)

Формат работы
onsite
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
Singapore
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Process Control Defectivity Engineer (Semiconductor Manufacturing): Analyzing and reducing wafer defects in high-volume semiconductor manufacturing through SEMVision review, automatic defect classification, EDX analysis, and yield correlation with an accent on defect characterization, failure analysis, and process integration. Focus on tracing yield-impacting defects to process steps, tools, or chambers, confirming mechanisms through FA, and implementing corrective actions with cross-functional engineering teams.

Location: Singapore, Singapore

Company

hirify.global develops materials science and engineering solutions, equipment, and services for semiconductor and advanced display manufacturing.

What you will do

  • Operate SEMVision defect review SEM systems to inspect defects and capture high-resolution images of defect morphology.
  • Classify defects manually and with Automatic Defect Classification, including building and maintaining classification recipes and libraries.
  • Analyze defect Pareto charts, wafer maps, spatial signatures, inline metrology, electrical test, and yield data to identify yield limiters.
  • Trace defects to source process steps, tools, or chambers using commonality analysis, inline data, and experiments.
  • Define and interpret follow-up failure analysis using FIB, TEM, STEM/EDS, Auger, SIMS, and related techniques.
  • Partner with process integration and module teams to implement corrective actions, qualify tools, monitor baselines, and verify defect reduction.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or a related field.
  • 2+ years of experience in semiconductor defect review, yield, process, or failure-analysis engineering preferred; relevant internships or research may be considered for strong new graduates.
  • Working knowledge of semiconductor process integration, including lithography, etch, deposition, CMP, implant, and clean processes.
  • Knowledge of yield analysis concepts such as defect density, kill ratio, defect Pareto, wafer-map signatures, and yield-defect correlation.
  • Experience with SEM or defect review SEM systems, FA techniques, and tools such as JMP, Excel, or yield-management systems.
  • Strong analytical, problem-solving, communication, and cross-functional collaboration skills.

Culture & Benefits

  • Supportive environment focused on learning, professional development, and career growth.
  • Work with R&D and engineering teams on semiconductor and display technologies.
  • Health and wellbeing programs and employee support.
  • Travel is required approximately 20% of the time.
  • Full-time regular employment; relocation is not available.

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