7 дней назад
Senior Verification Engineer (AI)
75 200 - 117 500€
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Verification Engineer (AI): Developing and verifying complex hardware IPs and subsystems for NIC, IPU, ASIC, and AI products with an accent on scalable verification environments, simulation, formal verification, and AI-assisted workflows. Focus on leading verification planning, closing functional and code coverage, debugging pre-silicon designs, and mentoring engineers across architecture, design, and software teams.
Location: Leixlip, Ireland; hybrid work model with time split between the assigned site and off-site work.
Annual salary: €75,200–€117,500.
Company
's Central Engineering Group designs and verifies IPs and architectures for NIC, IPU, ASIC, networking, AI, cloud, and other specialized workloads.
What you will do
- Own verification planning and execution for key IP features and subsystem integration points.
- Build scalable verification environments with reusable test benches, checkers, VIPs, behavioral models, and targeted test plans.
- Use simulation and formal property verification to identify and resolve pre-silicon bugs and achieve coverage closure.
- Collaborate with architecture, design, and software teams from specification through bring-up.
- Lead IP delivery, functional sign-offs, and verification of performance and power metrics across multiple customers.
- Mentor verification engineers and establish team-level verification best practices, including AI-assisted development and ML-driven verification flows.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 10+ years of experience in functional design verification for ASIC, SoC, or FPGA designs.
- Expertise in SystemVerilog, OVM/UVM, debugging tools, IP test environments, and/or formal verification.
- Strong knowledge of digital design fundamentals and microarchitecture principles.
- Experience with formal property verification, SystemVerilog Assertions, and code and functional coverage analysis is preferred.
- Experience with Ethernet, IPsec, DTLS, MACsec, AMBA APB/AXI, SystemC, Python, Perl, or shell scripting is preferred.
Nice to have
- Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Experience collaborating across teams to drive architectural improvements.
- Practical use of AI tools in pre-silicon design verification workflows.
Culture & Benefits
- Hybrid work model combining on-site and off-site work.
- Work in an agile, highly skilled design and verification team.
- Opportunities to contribute to advanced silicon and system innovation across networking, cloud, and AI workloads.
- Total compensation package with additional pay components and benefits potentially included.
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