Senior CPU Silicon Analysis Engineer

Location: On-site in Hillsboro, Oregon, United States

Annual salary: $190,610–$269,100 USD

Company

hirify.global's architecture team develops and evaluates CPU designs to guide future processor roadmap decisions.

What you will do

• Own and operate lab infrastructure for silicon bring-up, maintenance, debugging, and characterization of pre-production and production platforms.
• Plan and execute measurements covering performance, IPC, power, dynamic capacitance, leakage, voltage-frequency curves, and microarchitectural telemetry.
• Design measurement campaigns across varied workloads, operating conditions, and thermal and power envelopes.
• Analyze silicon data to identify power and performance gaps, anomalies, and opportunities against architectural expectations and roadmap targets.
• Collaborate with architecture, benchmarking, backend design, and simulation teams to correlate lab results with models and design data and resolve root causes.
• Develop scripts, tooling, and automation for data collection, processing, and reporting, and communicate findings through technical reports and presentations.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline with 8+ years of relevant industry experience, or a related master's degree with 6+ years of relevant industry experience.
• Hands-on experience with silicon lab environments, platform bring-up, debugging, and instrumentation.
• Experience collecting and analyzing silicon power and performance metrics, including IPC, frequency, dynamic capacitance, leakage, and microarchitectural telemetry.
• Proficiency in Python, Bash, or similar scripting languages for test automation and data analysis.
• Strong analytical, detail-oriented, collaborative, and technical communication skills.
• Ability to work on-site in Hillsboro, Oregon, United States.

Nice to have

• CPU silicon characterization across multiple designs and operating conditions.
• EMON/PMU-based performance profiling and OS-level performance tooling.
• CPU microarchitecture knowledge for interpreting performance counters and correlating measurements with architectural behavior.
• Backend design knowledge, including voltage-frequency corner selection, leakage-frequency tradeoffs, and process library characteristics.
• RTL simulation, pre-silicon performance modeling, silicon benchmarking, and performance characterization experience.

Culture & Benefits

• On-site work model with Shift 1 scheduling.
• Health, retirement, and vacation benefits.
• Competitive pay and stock bonuses.
• Collaboration with architecture, design, benchmarking, and simulation stakeholders.