AI Silicon, DFT Engineer

Location: Mountain View, California, or remote within the United States

Company

hirify.global develops semiconductor-based computing platforms designed to improve the energy efficiency of AI hardware.

What you will do

• Lead DFT architecture and implementation using scan compression, MBIST, JTAG, and boundary scan.
• Drive hierarchical DFT for large-scale SoCs, including core-level wrapping, pattern retargeting, and top-level integration.
• Own DFT strategy, defect analysis, yield improvement, and foundry interface activities for test chips.
• Develop test methodologies for 2.5D/3D stacked-die systems, die-to-die interfaces, and IEEE 1838-based architectures.
• Integrate test strategies for custom analog and mixed-signal macros within digital designs.
• Own ATPG, fault simulation, test-vector validation, STA, timing closure, and final DFT sign-off.

Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of digital DFT and test-architecture experience, including successful tapeouts on modern process nodes; 7nm, 5nm, or newer preferred.
• Deep expertise in scan compression, MBIST, fault modeling, ATPG, and test reliability for advanced-node designs.
• Expertise in STA and timing closure for shift and capture test modes.
• Expert-level proficiency with EDA CAD tools and strong scripting skills in Tcl, Python, or Perl.
• Excellent written and verbal communication skills, including management of external vendor or design-house deliverables.

Nice to have

• Experience with die-to-die interconnect testing, chiplets, and 3D-IC DFT architectures.
• Test-architecture experience for machine-learning accelerators or large-scale systolic arrays.
• Experience integrating custom analog macros and complex power-sequencing requirements.
• Familiarity with AI tools for accelerating chip design.

Culture & Benefits

• Work as a foundational member of a multidisciplinary R&D team.
• Collaborate across architecture, digital design, analog design, foundry interfaces, and external partners.
• Contribute to design-flow automation and testability best practices aimed at first-pass silicon success.