Mixed Signal IC Layout Engineer (FinFET)

Location: Remote within the United States. The role is based in the United States and involves access to U.S. export-controlled technology.

Compensation for engineers ranges from $100,000 to $500,000, including base and variable compensation targets.

Company

Tenstorrent develops AI computing platforms combining software models, compilers, networking, platforms, semiconductors, and high-performance RISC-V CPUs.

What you will do

• Execute full-custom analog and mixed-signal layouts for PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, and high-speed I/Os.
• Develop block and top-level floorplans, placement, and routing for integration into a D2D PHY and larger SoCs.
• Optimize area, parasitics, matching, coupling, congestion, IR drop, and electromigration for precision, noise, timing, power, and reliability targets.
• Close physical verification requirements including DRC, LVS, ERC, DFM, and antenna checks.
• Support post-layout extraction and simulation and collaborate with circuit designers on complex mixed-signal blocks.
• Contribute to layout methodology and automation using Python, Tcl, SKILL, or similar scripting tools.

Requirements

• Experienced analog or mixed-signal IC layout engineer with a strong full-custom layout background on high-speed blocks.
• Proficiency with Synopsys Custom Compiler or Cadence Virtuoso and Synopsys ICV or Siemens Calibre.
• Deep experience with CMOS or FinFET nodes, ideally TSMC or Samsung 12nm–2nm, with delivered silicon.
• Strong understanding of EM/IR, ESD, latch-up, parasitic effects, matching, and physical verification.
• Ability to own complex blocks independently and collaborate effectively with circuit designers.
• Typically a BSEE or equivalent experience with approximately 10+ years in analog or mixed-signal layout.

Nice to have

• Experience with TSMC or Samsung advanced nodes down to 2nm.
• Experience developing layout automation and productivity scripts.

Culture & Benefits

• Work remotely from anywhere in the United States.
• Work on advanced AI computing and high-performance RISC-V technologies.
• Gain hands-on experience with advanced FinFET mixed-signal layout and D2D PHY integration.
• Help evolve layout flows, methodologies, and automation across the organization.
• Receive a competitive compensation and benefits package.

Hiring process

• The interview process assesses the appropriate experience level for the role.
• The final offer level is aligned with the assessment and may differ from the level stated in the posting.
• Employment is contingent on eligibility to access U.S. export-controlled technology.